AM79C989JCT Advanced Micro Devices, AM79C989JCT Datasheet - Page 19

• Manufacturer Part Number: AM79C989JCT
• Description: Quad Ethernet Switching Transceiver (QuEST)
• Manufacturer: Advanced Micro Devices

Port Registers
Nine physical registers in the QuEST device are allo-
cated per port. Six of the port registers relate to Auto-
Negotiation. The remaining port registers are used for
control.
Registers 0, 1, 4-7, and 18-20 require an exact match
to specify the port being addressed. A particular regis-
ter is addressed by sending the serial management
frame with the target address of the designated port.
The lower two bits of the PHYAD (bits A1 and A0) spec-
ify which port is selected.
Bit(s)
15
14
13
12
11
10
REGAD
9
2-3
16
17
Restart ANEG
Table 5. Shared Registers
ANEG_EN
Loopback
PWR_DN
Reserved
Reserved
SRESET
Name
Interrupt Enable and Status
Summary Status
Register Name
1 = Resets the Auto Negotiation Control and Status registers to
their default state;
0 = Has no effect.
After reset is completed (approximately 10 s), SRESET is cleared.
1 = Port will loop back the QTX_DATA to the QRX_DATA. Transmit
data will not be transmitted and receive data from the network will
be ignored.
0 = The port will receive and transmit normally.
Written and read as zero.
1 = Auto-Negotiation enabled.
0 = Auto-Negotiation disabled.
1 = 10BASE-T port Auto-Negotiation is reset. The Auto-Negotiation
process and Link Status State Machine will terminate. Link Test
Pulses will terminate.
0 = 10BASE-T port resumes normal operation.
Written and read as zero.
1 = Auto-Negotiation restarts. The bit will be cleared when the Auto-
Negotiation process completes.
0 = Has no effect.
Table 7. Auto-Negotiation Control Register (Reg 0)
Device ID
P R E L I M I N A R Y
Am79C989
Description
Non-Implemented Registers
Non-implemented registers should neither be written to
or read. Reserved register bits within defined registers
should be written with zeros. Reserved register bits
may return undefined data and should be masked
by software.
Auto-Negotiation Control Register (Reg 0)
The Auto-Negotiation Control Register (Reg 0) con-
tains Read/Write (R/W), Read/Only (R/O), and Self-
Clearing (SC) bits. This register is duplicated for each
port.
REGAD
18
19
20
0
1
4
5
6
7
Table 6. Port Registers
Auto Negotiation Link Partner
Auto Negotiation Expansion
Auto Negotiation Next Page
Auto Negotiation Address
Auto Negotiation Control
Auto Negotiation Status
Register Name
Error Mask
Control
Status
R/W, SC
R/W, SC
Read/
Write
R/W
R/W
R/W
R/O
R/O
Default/
Reset
0
0
1
0
0
0
0
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