HIP0051IB Intersil Corporation, HIP0051IB Datasheet - Page 4

• Manufacturer Part Number: HIP0051IB
• Description: 0.25A/50V Octal Low Side Power Driver with Serial Bus Control
• Manufacturer: Intersil Corporation

Pin Descriptions
V
The V
the IC. The normal operating voltage range is 4.5 to 5.5V.
When switched on, the POR forces all outputs off.
SCK - Serial Clock
SCK is the clock input for the SPI interface. Output ON/OFF
control data is clocked into an eight stage shift register on
the rising edge of an external clock. This input has a Schmitt
trigger.
SI - Serial Data In
SI is the Serial Data Input pin for the SPI interface. The eight
Power Outputs are controlled by the serial data via the
Output Data Buffer. This input has a Schmitt trigger.
STR - Strobe for the SPI Interface
When the STR pin is high, data from the 8-bit shift register is
passed into the Output Data Buffers where it controls the
ON-OFF state of each output driver. The data is latched in
the Output Data Buffers on the trailing edge of the STR
pulse. This input has a Schmitt trigger.
CC
STROBE
- Logic Power Supply
CC
pin is the positive 5V logic voltage supply input for
D1
0
1
1
1
1
0
1
D2
0
0
1
1
1
0
1
8-BIT SERIAL DATA (LATCHED)
D3
0
0
0
1
1
0
1
D4
0
0
0
0
1
0
1
D5
0
0
0
0
0
1
1
OUTPUT CONTROL TABLE
D6
0
0
0
0
0
1
1
HIP0051
D7
0
0
0
0
0
1
1
4
SO - Serial Data Out
The Serial Data Out allows other ICs to be serially
cascaded. For example, a 10-bit LED driver may be located
behind the HIP0051. A controlling microprocessor may then
clock out 18 bits of information and simultaneously strobe
both parts. The cascaded ICs may be the same or different
from the HIP0051.
DR0 to DR7 - Outputs 0 Thru 7
The Drain Output pins of the DMOS Power Drivers are
capable of sinking 250mA.
EN - Enable
The Enable pin is an active low enable function for all eight
output drivers. When EN is high, drive from the Output Data
Buffer is held low and all output drivers are disabled. When
EN is low, the output drivers are enabled and data in the
8-bit shift register is transparent to the Output Data Buffer.
This input has a Schmitt trigger.
LGND and GND - Ground
LGND is the logic input power supply ground pin. The GND
pins are common grounds for the Power Output Drivers. The
power supplies for the logic and power circuits require a
common ground. To minimize ground bounce at the logic
input, the external ground return path for the GND pin should
be separate from the LGND pin. LGND and GND have com-
mon substrate ground connections on the chip.
D8
0
0
0
0
0
1
1
DR1
OFF
OFF
ON
ON
ON
ON
ON
DR2
OFF
OFF
OFF
ON
ON
ON
ON
DR3
OFF
OFF
OFF
OFF
ON
ON
ON
DR4
OFF
OFF
OFF
OFF
OFF
ON
ON
OUTPUT
DR5
OFF
OFF
OFF
OFF
OFF
ON
ON
DR6
OFF
OFF
OFF
OFF
OFF
ON
ON
DR7
OFF
OFF
OFF
OFF
OFF
ON
ON
DR8
OFF
OFF
OFF
OFF
OFF
ON
ON