K4T51043Q Samsung, K4T51043Q Datasheet - Page 28

• Manufacturer Part Number: K4T51043Q
• Description: 512Mb B-die DDR2 SDRAM
• Manufacturer: Samsung

512Mb B-die DDR2 SDRAM
31. Input waveform timing is referenced from the input signal crossing at the V
and V
32. Input waveform timing is referenced from the input signal crossing at the V
and V
33. tWTR is at lease two clocks (2 * tCK) independent of operation frequency.
34. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input
signal crossing at the VIH(ac) level to the single-ended data strobe crossing VIH/L(dc) at the start of its tran-
sition for a rising signal, and from the input signal crossing at the VIL(ac) level to the single-ended data strobe
crossing VIH/L(dc) at the start of its transition for a falling signal applied to the device under test. The DQS
signal must be monotonic between Vil(dc)max and Vih(dc)min.
35. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input
signal crossing at the VIH(dc) level to the single-ended data strobe crossing VIH/L(ac) at the end of its transi-
tion for a rising signal, and from the input signal crossing at the VIL(dc) level to the single-ended data strobe
crossing VIH/L(ac) at the end of its transition for a falling signal applied to the device under test. The DQS
signal must be monotonic between Vil(dc)max and Vih(dc)min.
36. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE
must remain at the valid input level the entire time it takes to achieve the 3 clocks of registeration. Thus, after
any cKE transition, CKE may not transitioin from its valid level during the time period of tIS + 2*tCK + tIH.
IL(ac)
IL(dc)
for a falling signal applied to the device under test.
for a falling signal applied to the device under test.
CK
CK
tIS
tIH
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tIS
tIH
V
V
V
V
V
V
V
IH(ac)
IH(dc)
DDQ
IH(ac)
IH(dc)
REF(dc)
IL(dc)
IL(ac)
SS
level for a rising signal
level for a rising signal
max
max
min
min
Rev. 1.4 Feb. 2005
DDR2 SDRAM