K4T51043Q Samsung, K4T51043Q Datasheet - Page 3

• Manufacturer Part Number: K4T51043Q
• Description: 512Mb B-die DDR2 SDRAM
• Manufacturer: Samsung

512Mb B-die DDR2 SDRAM
0. Ordering Information
Note : Speed bin is in order of CL-tRCD-tRP
1.Key Features
Note : This data sheet is an abstract of full DDR2 specification and does not cover the common features which are
described in “Samsung’s DDR2 SDRAM Device Operation & Timing Diagram”
CAS Latency
tRCD(min)
tRP(min)
tRC(min)
• JEDEC standard 1.8V ± 0.1V Power Supply
• VDDQ = 1.8V ± 0.1V
• 200 MHz f
• 4 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5
• Programmable Additive Latency: 0, 1 , 2 , 3 and 4
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Average Refesh Period 7.8us at lower then T
• Package: 60ball FBGA - 128Mx4/64Mx8 , 84ball FBGA
• All of Lead-free products are compliant for RoHS
Organization
128Mx4
32Mx16
533Mb/sec/pin
data-strobe is an optional feature)
3.9us at 85°C < T
- 32Mx16
64Mx8
Speed
CK
for 400Mb/sec/pin, 267MHz f
K4T51043QB-GCD5
K4T51083QB-GCD5
K4T51043QB-ZCD5
K4T51083QB-ZCD5
K4T51163QB-GCD5
K4T51163QB-ZCD5
DDR2-533 4-4-4
CASE
DDR2-533
4-4-4
< 95 °C
15
15
55
4
DDR2-400
3-3-3
15
15
55
3
K4T51043QB-GCCC
K4T51083QB-GCCC
K4T51163QB-GCCC
K4T51043QB-ZCCC
K4T51083QB-ZCCC
K4T51163QB-ZCCC
DDR2-400 3-3-3
CK
CASE
for
Units
tCK
ns
ns
ns
Page 3 of 29
85°C,
The 512Mb DDR2 SDRAM is organized as a 32Mbit x 4
I/Os x 4 banks, 16Mbit x 8 I/Os x 4banks or 8Mbit x 16 I/Os
x 4 banks device. This synchronous device achieves high
speed
533Mb/sec/pin (DDR2-533) for general applications.
The chip is designed to comply with the following key
DDR2 SDRAM features such as posted CAS with additive
latency, write latency = read latency -1, Off-Chip
Driver(OCD) impedance adjustment and On Die Termina-
tion.
All of the control and address inputs are synchronized with
a pair of externally supplied differential clocks. Inputs are
latched at the crosspoint of differential clocks (CK rising
and CK falling). All I/Os are synchronized with a pair of
bidirectional strobes (DQS and DQS) in a source synchro-
nous fashion. The address bus is used to convey row, col-
umn, and bank address information in a RAS/CAS
multiplexing style. For example, 512Mb(x4) device receive
14/11/2 addressing.
The 512Mb DDR2 device operates with a single
1.8V ± 0.1V power supply and 1.8V ± 0.1V VDDQ.
The
FBGAs(x4/x8) and in 84ball FBGAs(x16).
Note: The functionality described and the timing specifica-
tions included in this data sheet are for the DLL Enabled
mode of operation.
512Mb
Lead-Free
Lead-Free
Lead-Free
double-data-rate
Package
Leaded
Leaded
Leaded
DDR2
device
transfer
is
Rev. 1.4 Feb. 2005
DDR2 SDRAM
available
rates
of
in
up
60ball
to