AM53CF94 Advanced Micro Devices, AM53CF94 Datasheet - Page 18

• Manufacturer Part Number: AM53CF94
• Description: Enhanced SCSI-2 Controller (ESC)
• Manufacturer: Advanced Micro Devices

FIFO Register (02H) Read/Write
FFREG – Bits 7:0 – FF 7:0 – FIFO 7:0
The FIFO on the Am53CF94/96 is 16 bytes deep and is
used to transfer SCSI data to and from the ESC. The
bottom of the FIFO may be accessed via a read or write
to this register. This is the only register that can also be
accessed by DACK along with DMARD or DMAWR or
with REQ or ACK. This register is reset to zero by hard-
ware or software reset, or at the start of a selection or
reselection sequence, or if Clear FIFO command is
issued.
Command Register (03H) Read/Write
Command Register
CMDREG
18
FIFO Register
FFREG
DMA
7
x
FF7
7
0
AMD
CMD6
6
x
FF6
6
0
CMD5
5
x
FF5
5
0
CMD4
FF4
4
x
4
0
CMD3
FF3
3
0
3
x
CMD2
FF2
2
0
2
x
Type: Read/Write
Type: Read/Write
CMD1
FF1
1
0
Address: 02
1
x
Address: 03
Command 6:0
Direct Memory
Access
Am53CF94/Am53CF96
P R E L I M I N A R Y
17348B-18
17348B-19
FF0
0
0
CMD0
0
x
H
H
Commands to the ESC are issued by writing to this reg-
ister which is two bytes deep. Commands may be
queued, and will be read from the bottom of the queue.
At the completion of the bottom command, the top com-
mand, if present, will drop to the bottom of the register to
begin execution. All commands are executed within six
clock cycles of dropping to the bottom of the Command
Register, with the exception of the Reset SCSI Bus, Re-
set Device, and DMA Stop commands. These com-
mands are not queued and are executed within four
clock cycles of being loaded into the top this register.
Interrupts are sometimes generated upon command
completion. Should both commands generate inter-
rupts, and the first interrupt has not been serviced, the
interrupt from the second (top) command will be stacked
behind the first. The Status Register, Interrupt Register,
and Internal State Register will be updated to apply to
the second interrupt after the microprocessor services
the first interrupt.
Reading this register will return the command currently
being executed (or the last command executed if there
are no pending commands). When this register is
cleared, existing commands will be terminated and any
queued commands will be ignored. However, it does not
reset the register bits to ‘00H’.
CMDREG – Bit 7 – DMA – Direct Memory Access
When set, this bit notifies the device that the command
is a DMA instruction, when reset it is a non-DMA instruc-
tion. For DMA instructions the Current Transfer Count
Register (CTCREG) will be loaded with the contents of
the Start Transfer Count Register (STCREG). The data
is then transferred and the CTCREG is decremented for
each byte until it reaches zero.
CMDREG – Bits 6:0 – CMD 6:0 – Command 6:0
These command bits decode the commands that the
device needs to perform. There are a total of 31 com-
mands grouped into four categories. The groups are
Initiator Commands, Target Commands, Selection/
Reselection Commands and General Purpose Com-
mands.