CDP1871 Intersil Corporation, CDP1871 Datasheet
CDP1871
Available stocks
Related parts for CDP1871
CDP1871 Summary of contents
Page 1
... Three-State Outputs • Scans and Generates Code for 53 Key ASCII Keyboard Plus 32 HEX Keys (SPST Mechanical Contact Switches) • Shift, Control, and Alpha Lock Input • RC-Controlled Debounce Circuitry • Single Supply 4V to 10. (CDP1871A 6. (CDP1871AC) • N-Key Lockout Ordering Information PACKAGE TEMP ...
Page 2
... MRD CS4 34 TPB TPB CDP1800-SERIES CPU V DD SHIFT 39 SHIFT CONTROL 38 CONTROL ALPHA LOCK 37 ALPHA NORMAL BUS0-BUS7 8 BIT DATA BUS FIGURE 1. TYPICAL CDP1800 SERIES MICROPROCESSOR SYSTEM USING THE CDP1871A CS1 21 SCAN CLOCK CS CS2 22 23 CS3 24 CS4 CONTROL 34 TPB LOGIC KEY V DETECT DD F/F R DEBOUNCE ...
Page 3
... Absolute Maximum Ratings (All Voltages Referenced to V Terminal) SS CDP1871A -0.5V to +11V CDP1871AC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0. Input Current, any One Input CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specifi ...
Page 4
... CDP1871A, CDP1871ACCDP1871A, CDP1871AC Static Electrical Specifications PARAMETER (V) Output High Drive (Source) I 4.6 OH Current 9.5 Input Low Voltage V 0.5, 4.5 IL (Except Debounce Input High Voltage V 0.5, 4.5 IH (Except Debounce Debounce Schmitt Trigger V 0.4 D Input Voltage Positive Trigger Voltage 0.5 Negative Trigger Voltage V 0 ...
Page 5
... TPB output of the CDP1800-series microprocessor. RPT (Output): The repeat output flag which is used to indicate that a key is still closed after data has been read from the CDP1871A (DA = high). It remains low as long as the key is closed and is used for an autorepeat function, under CPU control. This output is normally connected to a fl ...
Page 6
... CONTROL overrides SHIFT and ALPHA 2. Showing ASCII outputs for all combinations with and without SHIFT, ALPHA LOCK and CONTROL. 3. Drive lines and 11 generate non-ASCII hex values which can be used for special codes. CDP1871A, CDP1871AC TABLE 2. VALID N-LINE CONNECTIONS CDP1871A SIGNAL CS3 CS2 N2 N0 ...
Page 7
... Operation The CDP1871A is made up of two major sections: the counter/scan-selection logic and the control logic (Figure 2). The counter and scan-selection logic scans the keyboard array using the drive lines (D1-D11) and the sense lines (S1- S8). The outputs of the internal 5-stage scancounter are ...
Page 8
... DD 4- This X X CDP1871ACD, CDP1871ACE (NOTE 1) MIN TYP MAX UNITS - - - Note Note 2 100 260 500 150 850 1900 ...
Page 9
... DA RPT DEBOUNCE D1-D11 PRESENT COUNT CS (NOTE) t CDV BUS0-BUS7 NOTE CS1 CS2 CS3 CS4 CS1, CS2, CS3 = (CPU N-LINES) CS4 (MRD) is High for CPU Input Instruction FIGURE 4. FIGURE 4. CDP1871A DYNAMIC TIMING DIAGRAM (REPEAT) CDP1871A, CDP1871AC OPEN CLOSED t DAH t RPH t RPL ...
Page 10
... FIGURE 5. TYPICAL SYSTEM SOFTWARE FLOWCHART FOR CDP1871A, CDP1871AC All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...