K6F2008V2E-LF55 Samsung semiconductor, K6F2008V2E-LF55 Datasheet - Page 2
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K6F2008V2E-LF55
Manufacturer Part Number
K6F2008V2E-LF55
Description
256Kx8 bit Super Low Power and Low Voltage Full CMOS Static RAM
Manufacturer
Samsung semiconductor
Datasheet
1.K6F2008V2E-LF55.pdf
(9 pages)
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
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Company:
Part Number:
K6F2008V2E-LF55
Manufacturer:
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K6F2008V2E Family
PIN DESCRIPTION
256Kx8 bit Super Low Power and Low Voltage Full CMOS Static RAM
FEATURES
• Process Technology: Full CMOS
• Organization: 256Kx8
• Power Supply Voltage: 3.0 ~ 3.6V
• Low Data Retention Voltage: 1.5V(Min)
• Three State Outputs
• Package Type: 32-TSOP1-0813.4F, 32-TSOP1-0813.4F(LF)
PRODUCT FAMILY
1. The parameter is measured with 30pF test load.
2. Typical values are measured at V
K6F2008V2E-F
Product Family
CS
A
Name
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
0
WE
OE
1
~A
VCC
, CS
CS2
A13
A15
A17
A14
A12
A11
A16
WE
A9
A7
A6
A5
A4
A8
17
2
Chip Select Input
Output Enable
Write Enable Input
Address Inputs
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Function
Operating Temperature
Industrial(-40~85 C)
Type1-Forward
32-sTSOP
CC
I/O
=3.3V, T
Name
DNU
Vcc
Vss
1
~I/O
8
A
=25 C and not 100% tested.
Data Inputs/Outputs
Power
Ground
Do Not Use
Vcc Range
Function
3.0~3.6V
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
Speed(ns)
55
1)
/70ns
2
GENERAL DESCRIPTION
advanced Full CMOS process technology. The families support
industrial temperature ranges for user flexibility of system
design. The families also supports low data retention voltage for
battery back-up operation with low data retention current.
FUNCTIONAL BLOCK DIAGRAM
The K6F2008V2E families are fabricated by SAMSUNG s
CS1
CS2
WE
OE
I/O
I/O
1
8
(I
Standby
SB1
Control
logic
0.5 A
Power Dissipation
, Typ)
2)
Clk gen.
(I
Operating
CC1
Data
cont
Data
cont
Row
select
3mA
, Max)
32-TSOP1-0813.4F
32-TSOP1-0813.4F(LF)
CMOS SRAM
Precharge circuit.
Memory array
1024 rows
256x8 columns
Column select
Address
I/O Circuit
PKG Type
Revision 1.1
May 2003