K7A801800 Samsung semiconductor, K7A801800 Datasheet
K7A801800
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K7A801800 Summary of contents
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... K7A403600B K7A403200B K7A401800B Document Title 128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No History 0.0 1. Initial draft 0.1 1. Changed DC parameters Icc ; from 350mA to 290mA at -16, from 330mA to 270mA at -15, from 300mA to 250mA at -14 from 100mA to 80mA SB1 0.2 1. Delete Pass-Through ...
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... K7A403600B K7A403200B K7A401800B 4Mb SB/SPB Synchronous SRAM Ordering Information Org. Part Number K7B401825B-QC(I)65/75/80 256Kx18 K7A401800B-QC(I)16/14 K7A401809B-QC(I)30/27/25/22/20 K7B403225B-QC(I)65/75/80 K7A403200B-QC(I)16/14 128Kx32 K7A403209B-QC(I)30/27/25/22/20 K7A403201B-QC(I)16/14 K7B403625B-QC(I)65/75/80 K7A403600B-QC(I)16/14 128Kx36 K7A403609B-QC(I)30/27/25/22/20 K7A403601B-QC(I)16/14 128Kx36/x32 & 256Kx18 Synchronous SRAM Speed Mode VDD FT ; Access Time(ns) Pipelined ; Cycle Time(MHz) SB 3.3 6.5/7.5/8.0 ns SPB(2E1D) 3 ...
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... K7A403600B K7A403200B K7A401800B 128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Pipelined Burst SRAM FEATURES • Synchronous Operation. • 2 Stage Pipelined operation with 4 Burst. • On-Chip Address Counter. • Self-Timed Write Cycle. • On-Chip Address and Control Registers. • 3.3V+0.3V/-0.165V Power Supply. DD • V Supply Voltage 3 ...
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... Chip Select 2 WEx Byte Write Inputs (x=a,b,c,d) OE Output Enable GW Global Write Enable BW Byte Write Enable ZZ Power Down Input LBO Burst Mode Control 128Kx36/x32 & 256Kx18 Synchronous SRAM 100 Pin TQFP (20mm x 14mm) K7A403600B(128Kx36) K7A403200B(128Kx32) TQFP PIN NO. SYMBOL PIN NAME 32,33,34,35,36,37 V Power Supply(+3.3V) DD 44,45,46,47,48,49 V Ground ...
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... CS Chip Select 2 WEx Byte Write Inputs (x=a,b) OE Output Enable GW Global Write Enable BW Byte Write Enable ZZ Power Down Input LBO Burst Mode Control 128Kx36/x32 & 256Kx18 Synchronous SRAM 100 Pin TQFP (20mm x 14mm) K7A401800B(256Kx18) TQFP PIN NO. SYMBOL 32,33,34,35,36,37, V Power Supply(+3.3V) DD 44,45,46,47,48,49, V Ground SS 50,80,81,82,99,100 N.C. No Connect ...
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... The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with ADV. When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally. ...
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... Notes : 1. X means "Don t Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK( ). 128Kx36/x32 & 256Kx18 Synchronous SRAM WRITE CLK ADDRESS ACCESSED ...
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... Supply Voltage V DDQ Ground V * The above parameters are also guaranteed at industrial temperature range. CAPACITANCE* (T =25 C, f=1MHz) A PARAMETER SYMBOL Input Capacitance C Output Capacitance C *Note : Sampled not 100% tested. 128Kx36/x32 & 256Kx18 Synchronous SRAM SYMBOL DDQ STG Commercial T OPR ...
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... Input Rise and Fall Time(Measured at 0.3V and 2.1V for 2.5V I/O) Input and Output Timing Reference Levels for 3.3V I/O Input and Output Timing Reference Levels for 2.5V I/O Output Load * The above parameters are also guaranteed at industrial temperature range. 128Kx36/x32 & 256Kx18 Synchronous SRAM ( =3.3V+0.3V/-0.165V) A ...
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... Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled. 4. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state. 128Kx36/x32 & 256Kx18 Synchronous SRAM Output Load(B) (for t RL=50 VL=1 ...
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... K7A403600B K7A403200B K7A401800B 128Kx36/x32 & 256Kx18 Synchronous SRAM - 11 - Nov 2001 Rev 1.0 ...
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... K7A403600B K7A403200B K7A401800B 128Kx36/x32 & 256Kx18 Synchronous SRAM - 12 - Nov 2001 Rev 1.0 ...
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... K7A403600B K7A403200B K7A401800B 128Kx36/x32 & 256Kx18 Synchronous SRAM - 13 - Nov 2001 Rev 1.0 ...
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... K7A403600B K7A403200B K7A401800B 128Kx36/x32 & 256Kx18 Synchronous SRAM - 14 - Nov 2001 Rev 1.0 ...
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... K7A403600B K7A403200B K7A401800B 128Kx36/x32 & 256Kx18 Synchronous SRAM - 15 - Nov 2001 Rev 1.0 ...
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... K7A403600B K7A403200B K7A401800B APPLICATION INFORMATION DEPTH EXPANSION The Samsung 128Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion. This permits easy secondary cache upgrades from 128K depth to 256K depth without extra logic. Data Address A [0:17] CLK 64-Bits ...
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... K7A403600B K7A403200B K7A401800B APPLICATION INFORMATION DEPTH EXPANSION The Samsung 256Kx18 Synchronous Pipelinde Burst SRAM has two additional chip selects for simple depth expansion. This permits easy secondary cache upgrades from 256K depth to 512K depth without extra logic. Data Address A [0:18] CLK Microprocessor ...
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... K7A403600B K7A403200B K7A401800B PACKAGE DIMENSIONS 100-TQFP-1420A #1 0.65 128Kx36/x32 & 256Kx18 Synchronous SRAM 22.00 0.30 20.00 0.20 16.00 14.00 (0.83) (0.58) 0.30 0.10 0.10 MAX 1.40 0.10 0.05 MIN 0.50 0. Units ; millimeters/Inches 0~8 + 0.10 0.127 - 0.05 0.30 0.10 MAX 0.20 0.50 0.10 1.60 MAX Nov 2001 Rev 1.0 ...