K7A801800 Samsung semiconductor, K7A801800 Datasheet - Page 3

• Manufacturer Part Number: K7A801800
• Description: 256Kx36 & 512Kx18-Bit Synchronous Pipelined Burst SRAM
• Manufacturer: Samsung semiconductor

K7A403600B
K7A403200B
K7A401800B
LOGIC BLOCK DIAGRAM
128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Pipelined Burst SRAM
FEATURES
FAST ACCESS TIMES
ADSC
• Synchronous Operation.
• 2 Stage Pipelined operation with 4 Burst.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• V
• V
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a linear
• Three Chip Enables for simple depth expansion with No Data Cont-
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-TQFP-1420A .
• Operating in commeical and industrial temperature range.
ADSP
Cycle Time
Clock Access Time
Output Enable Access Time
DQPa ~ DQPd
(x=a,b,c,d or a,b)
DQa0 ~ DQd7
or 2.5V+0.4V/-0.125V for 2.5V I/O.
ADV
WEx
LBO
burst.
nention ; 2cycle Enable, 1cycle Disable.
CLK
CS1
CS2
CS2
GW
BW
DD
OE
ZZ
DDQ
= 3.3V+0.3V/-0.165V Power Supply.
Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O
PARAMETER
or DQa0 ~ DQb7
DQPa ~ DQPb
BURST CONTROL
Symbol
tCYC
tCD
tOE
CONTROL
LOGIC
LOGIC
or A0~A17
128Kx36/x32 & 256Kx18 Synchronous SRAM
-16
6.0
3.5
3.5
A0~A16
-14
7.2
4.0
4.0
Unit
- 3 -
ns
ns
ns
ADDRESS
REGISTER
A0~A1
GENERAL DESCRIPTION
The K7A403600B, K7A403200B and K7A401800B are
4,718,592-bit Synchronous Static Random Access Memory
designed for high performance second level cache of Pen-
tium and Power PC based System.
It is organized as 128K(256K) words of 36(18) bits and inte-
grates address and control registers, a 2-bit burst address
counter and added some new functions for high perfor-
mance cache RAM applications; GW, BW, LBO, ZZ. Write
cycles are internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is
performed by the combination of WEx and BW when GW is
high. And with CS
Burst cycle can be initiated with either the address status
processor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated inter-
nally in the system s burst sequence and are controlled by
the burst address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(lin-
ear or interleaved).
ZZ pin controls Power Down State and reduces Stand-by
current regardless of CLK.
The K7A403600B, K7A403200B and K7A401800B are fab-
ricated using SAMSUNG s high performance CMOS tech-
nology and is available in a 100pin TQFP package. Multiple
power and ground pins are utilized to minimize ground
bounce.
COUNTER
ADDRESS
BURST
36/32 or 18
or A2~A17
A2~A16
A 0~A 1
1
high, ADSP is blocked to control signals.
REGISTER
OUTPUT
BUFFER
128Kx36/32 , 256Kx18
MEMORY
ARRAY
REGISTER
DATA-IN
Nov 2001
Rev 1.0