CX28398 Conexant Systems, CX28398 Datasheet - Page 216
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CX28398
Manufacturer Part Number
CX28398
Description
(CX28394 - CX28398) Quad/x16/Octal?T1/E1/J1 Framers
Manufacturer
Conexant Systems
Datasheet
1.CX28398.pdf
(305 pages)
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3.0 Registers
3.16 System Bus Registers
3.16 System Bus Registers
X2CLK
SBI_OE
EMF
EMBED
3-94
0D0—System Bus Interface Configuration (SBI_CR)
X2CLK
7
Enable Times 2 Clocks—X2CLK modifies the number of RSB/TSB clock cycles used to
clock a single data bit onto RSB and TSB. When X2CLK is active, two RSBCKI/TSBCKI
clock cycles occur for each RPCMO, RSIGO, SIGFRZ, TPCMI, and TSIGI bit. But the
FSYNC and MSYNC signals remain at the full 1x RSBCKI/TSBCKI clock rate.
Enable System Bus Outputs—Places RPCMO, RSIGO, RINDO, and SIGFRZ output buffers
under the control of the RSB timebase. SBI_OE also places the TINDO output buffer under
the control of TSB timebase. Inactive (low) forces SBI output buffers to a high-impedance
state. Power on and RESET [addr 001] force SBI_OE to an inactive state to avoid bus
contention on devices sharing system bus connections.
Embedded Framing—During T1 mode, EMF controls placement of T1 framing bits on
RPCMO and sampling of T1 framing bits from TPCMI according to the selected embedded
framing format. EMF supports system buses that carry T1 frames but operate above T1 line
rate. EMF allows the system bus to transport and maintain 193-bit frame integrity as T1 data is
passed through RSLIP and/or TSLIP buffers.
EMBED instructs the transmit framer (refer to [TABORT; addr 071]) to align the TX timebase
with respect to the frame and multiframe alignment embedded in the transmit line rate data
output from TSLIP (TXDATA). EMBED is required during applications that bypass frame
formatter [TFRM; addr 072] or Sa-bits [TMAN; addr 074]. If TSLIP is enabled, EMBED is
inactive, and overhead is bypassed, TX timebase is not guaranteed to align to TXDATA, and
bypassed overhead cannot reliably pass through TSLIP. EMBED is applicable to all system bus
modes.
SBI_OE
0 = RSB/TSB signals at RSBCKI/TSBCKI
1 = Two SBCKI clock cycles per SBI bit (except FSYNC and MSYNC).
0 = SBI outputs forced to high-impedance state
1 = SBI outputs controlled by respective RSB or TSB timebase
0 = G.802 embedded format
1 = Reserved embedded format
6
NOTE(S):
is in bypass or transparent mode.
EMBED
0
1
1
Embedded F-bits reach TX output only if frame formatter [TFRM; addr 072]
EMF
5
T1/E1N
X
0
1
EMBED
4
Conexant
G.802 embedded; search TXDATA
Transmit framer searches TPCMI
TS0 embedded; search TXDATA
Embedded Framing Mode
SBI[3]
3
SBI[2]
2
Quad/x16/Octal—T1/E1/J1 Framers
CX28394/28395/28398
SBI[1]
1
SBI[0]
100054E
0
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