K7A801809B Samsung semiconductor, K7A801809B Datasheet
K7A801809B
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K7A801809B Summary of contents
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... K7A803601M K7A801801M Document Title 256Kx36 & 512Kx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. History 0.0 Initial draft 0.1 Modify DC characteristics( Input Leakage Current test Conditions) form Max 0.2 Remove 119BGA Package Type. 0.3 Change DC Characteristics. I value from 65mA to 110mA at - value from 60mA to 110mA at -85 ...
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... K7A803601M K7A801801M 256Kx36 & 512Kx18-Bit Synchronous Pipelined Burst SRAM FEATURES • Synchronous Operation. • 2 Stage Pipelined operation with 4 Burst. • On-Chip Address Counter. • Self-Timed Write Cycle. • On-Chip Address and Control Registers. • 3.3V+0.165V/-0.165V Power Supply. • I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O • ...
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... The pin 42 is reserved for address bit for the 16Mb . 256Kx36 & 512Kx18 Synchronous SRAM 100 Pin TQFP (20mm x 14mm) K7A803601M(256Kx36) TQFP PIN NO. ...
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... The pin 42 is reserved for address bit for the 16Mb . 256Kx36 & 512Kx18 Synchronous SRAM 100 Pin TQFP (20mm x 14mm) K7A801801M(512Kx18) TQFP PIN NO. ...
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... The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with ADV. When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2cycles of wake up time ...
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... Note : 1. X means "Don t Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK( ). 256Kx36 & 512Kx18 Synchronous SRAM WRITE CLK ADDRESS ACCESSED ...
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... DDQ Ground V CAPACITANCE* (T =25 C, f=1MHz) A PARAMETER SYMBOL Input Capacitance C Output Capacitance C *Note : Sampled not 100% tested. 256Kx36 & 512Kx18 Synchronous SRAM PRESENT CYCLE OPERATION CS WRITE 1 Initiate Read Cycle Address=An L Data=Qn-1 for all bytes No new cycle H Data=Qn-1 for all bytes No new cycle ...
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... Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O) Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O) Input and Output Timing Reference Levels for 3.3V I/O Input and Output Timing Reference Levels for 2.5V I/O Output Load 256Kx36 & 512Kx18 Synchronous SRAM (V =3.3V+0.165V/-0.165V TEST CONDITIONS V =Max ...
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... Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled. 3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state any given voltage and temperature, t 256Kx36 & 512Kx18 Synchronous SRAM Output Load(B), (for t RL=50 VL=1 ...
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... K7A803601M K7A801801M 256Kx36 & 512Kx18 Synchronous SRAM - 10 - May 1999 Rev 3.0 ...
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... K7A803601M K7A801801M 256Kx36 & 512Kx18 Synchronous SRAM - 11 - May 1999 Rev 3.0 ...
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... K7A803601M K7A801801M 256Kx36 & 512Kx18 Synchronous SRAM - 12 - May 1999 Rev 3.0 ...
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... K7A803601M K7A801801M 256Kx36 & 512Kx18 Synchronous SRAM - 13 - May 1999 Rev 3.0 ...
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... K7A803601M K7A801801M 256Kx36 & 512Kx18 Synchronous SRAM - 14 - May 1999 Rev 3.0 ...
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... K7A803601M K7A801801M APPLICATION INFORMATION DEPTH EXPANSION The Samsung 256Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion. This permits easy secondary cache upgrades from 256K depth to 512K depth without extra logic. Data Address A [0:18] CLK Microprocessor CLK ...
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... K7A803601M K7A801801M APPLICATION INFORMATION DEPTH EXPANSION The Samsung 512Kx18 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion. This permits easy secondary cache upgrades from 512K depth to 1M depth without extra logic. Data Address A [0:19] CLK Microprocessor CLK ...
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... K7A803601M K7A801801M PACKAGE DIMENSIONS 100-TQFP-1420A 22.00 20.00 #1 0.65 256Kx36 & 512Kx18 Synchronous SRAM 0.30 0.20 16.00 0.30 14.00 0.20 (0.83) (0.58) 0.30 0.10 0.10 MAX 1.40 1.60 MAX 0.10 0.05 MIN 0.50 0. Units ; millimeters/Inches 0~8 + 0.10 0.127 - 0.05 0.10 MAX 0.50 0.10 May 1999 Rev 3.0 ...