AS7C251MPFS32A ALSC [Alliance Semiconductor Corporation], AS7C251MPFS32A Datasheet - Page 5
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AS7C251MPFS32A
Manufacturer Part Number
AS7C251MPFS32A
Description
2.5V 1M x 32/36 pipelined burst synchronous SRAM
Manufacturer
ALSC [Alliance Semiconductor Corporation]
Datasheet
1.AS7C251MPFS32A.pdf
(19 pages)
Signal descriptions
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to I
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, I
disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting
SNOOZE MODE during t
BW[a,b,c,d]
DQ[a,b,c,d]
2/14/05, v.1.3
CE1, CE2
A,A0,A1
ADSC
ADSP
GWE
ADV
BWE
CLK
LBO
CE0
Pin
OE
NC
ZZ
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
-
Properties
CLOCK
ASYNC
ASYNC
PUS
STATIC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
-
, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE.
Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock.
Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted.
Data. Driven as output when the chip is enabled and when OE is active.
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is inactive,
ADSP is blocked. Refer to the “Synchronous truth table” for more information.
Synchronous chip enables, active high, and active low, respectively. Sampled on clock edges when
ADSC is active or when CE0 and ADSP are active.
Address strobe processor. Asserted low to load a new address or to enter standby mode.
Address strobe controller. Asserted low to load a new address or to enter standby mode.
Advance. Asserted low to continue burst read/write.
Global write enable. Asserted low to write all 32/36 bits. When high, BWE and BW[a:d] control write
enable.
Byte write enable. Asserted low with GWE high to enable effect of BW[a:d] inputs.
Write enables. Used to control write of individual bytes when GWE is high and BWE is low. If any of
BW[a:d] is active with GWE high and BWE low, the cycle is a write cycle. If all BW[a:d] are inactive,
the cycle is a read cycle.
Asynchronous output enable. I/O pins are driven when OE is active and chip is in read mode.
Selects Burst mode. When tied to V
driven Low, device follows linear Burst order. This signal is internally pulled High.
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
No connect
SB2
is guaranteed after the time t
Alliance Semiconductor
ZZI
DD
®
is met. After entering SNOOZE MODE, all inputs except ZZ is
or left floating, device follows interleaved Burst order. When
Description
AS7C251MPFS32A
AS7C251MPFS36A
SB2
. The duration of
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