AS7C252MPFD18A-133TQC ALSC [Alliance Semiconductor Corporation], AS7C252MPFD18A-133TQC Datasheet - Page 4
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AS7C252MPFD18A-133TQC
Manufacturer Part Number
AS7C252MPFD18A-133TQC
Description
2.5V 2M x 18 pipelined burst synchronous SRAM
Manufacturer
ALSC [Alliance Semiconductor Corporation]
Datasheet
1.AS7C252MPFD18A-133TQC.pdf
(18 pages)
Functional description
The AS7C252MPFD18A is a high-performance CMOS 32-Mbit synchronous Static Random Access Memory (SRAM) device
organized as 2,097,152 words × 18 bits. It incorporates a two-stage register-register pipeline for highest frequency on any given
technology.
Fast cycle times of 5/6/7.5 ns with clock access times (t
Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller
address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally
generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip
address register when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In
a read operation, the data accessed by the current address registered in the address registers by the positive edge of CLK are
carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock
edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for the next
access of the burst when ADV is sampled low and both address strobes are high. Burst mode is selectable with the
With
uses a linear count sequence.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable
GWE writes all 18 bits regardless of the state of individual BW[a,b] inputs. Alternately, when GWE is high, one or more bytes
may be written by asserting BWE and the appropriate individual byte BWn signals.
BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are
disabled when BWn is sampled LOW regardless of OE. Data is clocked into the data input register when BWn is sampled low.
Address is incremented internally to the next burst address if BWn and ADV are sampled low. This device operates in double-
cycle deselect feature during read cycles.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC
and ADSP are as follows:
The AS7C252MPFD18A operates with a 2.5V
pin TQFP package.
TQFP capacitance
* Guaranteed not tested
TQFP thermal resistance
1 This parameter is sampled
• ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
• WE signals are sampled on the clock edge that samples ADSC low (and ADSP high).
• Master chip enable CE0 blocks ADSP, but not ADSC.
Input capacitance
I/O capacitance
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to top of case)
2/11/05,
LBO
Description
Parameter
unconnected or driven high, burst operations use an interleaved count sequence. With
v.1.1
1
1
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51
Symbol
C
C
I/O
IN
*
*
Alliance Semiconductor
± 5% power supply for the device core (V
Conditions
Test conditions
CD
V
) of 3.1/3.5/3.8 ns enable 200,167 and 133MHz bus frequencies.
V
OUT
IN
= 0V
= 0V
®
1–layer
4–layer
DD
)
. These devices are available in a 100-
Min
Symbol
-
-
θ
θ
θ
JA
JA
JC
AS7C252MPFD18A
LBO
driven low, the device
Typical
Max
40
22
5
7
8
4 of 18
LBO
Units
°C/W
°C/W
°C/W
Unit
pF
pF
input.