BS62LV8001DC55 BSI [Brilliance Semiconductor], BS62LV8001DC55 Datasheet

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BS62LV8001DC55

Manufacturer Part Number
BS62LV8001DC55
Description
Very Low Power CMOS SRAM 1M X 8 bit
Manufacturer
BSI [Brilliance Semiconductor]
Datasheet
n FEATURES
Ÿ Wide V
Ÿ Very low power consumption :
Ÿ High speed access time :
Ÿ Automatic power down when chip is deselected
Ÿ Easy expansion with CE1, CE2 and OE options
Ÿ Three state outputs and TTL compatible
Ÿ Fully static operation
Ÿ Data retention supply voltage as low as 1.5V
n POWER CONSUMPTION
n PIN CONFIGURATIONS
R0201-BS62LV8001
BS62LV8001DC
BS62LV8001EC
BS62LV8001FC
BS62LV8001EI
BS62LV8001FI
PRODUCT
Brilliance Semiconductor, Inc.
V
V
-55
-70
FAMILY
CC
CC
= 3.0V
= 5.0V
CC
A
B
C
D
E
F
G
H
operation voltage : 2.4V ~ 5.5V
CE1
DQ0
DQ1
VCC
VSS
DQ2
DQ3
A19
A18
A17
A16
A15
WE
NC
NC
NC
NC
A4
A3
A2
A1
A0
DQ0
VCC
DQ3
VSS
A18
NC
NC
NC
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
TEMPERATURE
Operation current : 31mA (Max.) at 55ns
Standby current :
Operation current : 76mA (Max.) at 55ns
Standby current :
55ns (Max.) at V
70ns (Max.) at V
-40
OPERATING
+0
DQ1
DQ2
OE
NC
NC
NC
NC
A8
Commercial
2
48-ball BGA top view
O
O
BS62LV8001EC
BS62LV8001EI
Industrial
C to +70
C to +85
A17
A14
A12
NC
A0
A3
A5
A9
3
A16
A15
A13
A10
A1
A4
A6
A7
O
Pb-Free and Green package materials are compliant to RoHS
O
4
Very Low Power CMOS SRAM
1M X 8 bit
C
C
CC
CC
DQ5
DQ6
CE1
: 3.0~5.5V
: 2.7~5.5V
WE
A11
NC
NC
A2
0.8uA (Typ.) at 25
10mA (Max.) at 1MHz
3.5uA (Typ.) at 25
5
V
2mA (Max.) at 1MHz
CC
25uA
50uA
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
=5.0V
CE2
DQ4
VCC
VSS
DQ7
A19
NC
NC
STANDBY
6
(I
CCSB1
A5
A6
A7
OE
CE2
A8
NC
NC
DQ7
DQ6
VSS
VCC
DQ5
DQ4
NC
NC
A9
A10
A11
A12
A13
A14
, Max)
V
4.0uA
8.0uA
reserves the right to change products and specifications without notice.
CC
=3.0V
O
O
C
C
10mA
1MHz
9mA
POWER DISSIPATION
1
V
n DESCRIPTION
The BS62LV8001 is a high performance, very low power CMOS
Static Random Access Memory organized as 1,048,576 by 8 bits
and operates form a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical CMOS standby
current of 0.8uA at 3.0V/25
3.0V/85
Easy memory expansion is provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2), and active LOW output
enable (OE) and three-state output drivers.
The BS62LV8001 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BS62LV8001 is available in DICE form, JEDEC standard 44-pin
TSOP II and 48-ball BGA package.
n BLOCK DIAGRAM
10MHz
39mA
40mA
CC
=5.0V
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CE1
CE2
A13
A17
A15
A18
A16
A14
A12
WE
OE
V
V
A7
A6
A5
A4
CC
SS
O
C.
75mA
76mA
f
Max.
Address
Buffer
Input
Operating
(I
Control
CC
8
, Max)
8
1.5mA
22
1MHz
2mA
O
Output
Buffer
Buffer
C and maximum access time of 55ns at
Data
Input
Data
Decoder
Row
V
10MHz
CC
19mA
20mA
=3.0V
8
8
BS62LV8001
2048
A11
30mA
31mA
f
Max.
A9
Address Input Buffer
A8
Column Decoder
Memory Array
2048 x 4096
Write Driver
Column I/O
Sense Amp
A3
Revision
May.
DICE
TSOP II-44
BGA-48-0912
TSOP II-44
BGA-48-0912
A2 A1 A0 A10
PKG TYPE
4096
512
18
2006
A19
2.3

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BS62LV8001DC55 Summary of contents

Page 1

Very Low Power CMOS SRAM bit Pb-Free and Green package materials are compliant to RoHS n FEATURES Ÿ Wide V operation voltage : 2.4V ~ 5.5V CC Ÿ Very low power consumption : V = 3.0V Operation ...

Page 2

PIN DESCRIPTIONS Name A0-A19 Address Input CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input WE Write Enable Input OE Output Enable Input DQ0-DQ7 Data Input/Output Ports TRUTH TABLE MODE CE1 H Not ...

Page 3

DC ELECTRICAL CHARACTERISTICS (T PARAMETER PARAMETER NAME V Power Supply CC V Input Low Voltage IL V Input High Voltage IH I Input Leakage Current IL I Output Leakage Current LO V Output Low Voltage OL V Output High ...

Page 4

LOW V DATA RETENTION WAVEFORM (2) (CE2 Controlled CE2 n AC TEST CONDITIONS (Test Load and Input/Output Reference) Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level ...

Page 5

SWITCHING WAVEFORMS (READ CYCLE) (1,2,4) READ CYCLE 1 ADDRESS D OUT (1,3,4) READ CYCLE 2 CE1 CE2 D OUT (1, 4) READ CYCLE 3 ADDRESS OE CE1 CE2 D OUT NOTES high in read Cycle. 2. ...

Page 6

AC ELECTRICAL CHARACTERISTICS (T WRITE CYCLE JEDEC PARANETER PARAMETER NAME NAME t t Write Cycle Time AVAX Chip Select to End of Write AVWL Address Set up Time AVWH Address ...

Page 7

WRITE CYCLE 2 ADDRESS CE1 CE2 WE D OUT D IN NOTES must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and ...

Page 8

ORDERING INFORMATION BS62LV8001 X Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in ...

Page 9

PACKAGE DIMENSIONS (continued) SIDE VIEW D 0.1 D1 3.375 VIEW A 48 mini-BGA (9mm x 12mm) R0201-BS62LV8001 NOTES: 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER ...

Page 10

Revision History Revision No. History 2.2 Add Icc1 characteristic parameter Improve Iccsb1 spec. I-grade from 110uA to 50uA at 5.0V C-grade from 55uA to 25uA at 5.0V 2.3 Change I-grade operation temperature range - from –25 O Change Iccdr ...

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