AS7C33256NTF32A ALSC [Alliance Semiconductor Corporation], AS7C33256NTF32A Datasheet
AS7C33256NTF32A
Related parts for AS7C33256NTF32A
AS7C33256NTF32A Summary of contents
Page 1
... Q D Address register Burst logic CLK D Write delay addr. registers CLK Control logic CLK 32/36 32/36 Data D Q Input Register CLK OE -75 8.5 7.5 300 120 30 Alliance Semiconductor AS7C33256NTF32A AS7C33256NTF36A TM DDQ Q 18 CLK 256K x 32/36 SRAM Array 32/36 32/36 32/36 Output Buffer OE 32/36 DQ[a,b,c,d] -85 -10 Units 10 12 8.5 10 280 240 mA 110 100 ...
Page 2
... PL-SCD PL-SCD PL-SCD PL-DCD PL-DCD PL-DCD NTD-PL NTD-PL NTD-PL NTD-FT NTD-FT NTD- Alliance Semiconductor AS7C33256NTF32A AS7C33256NTF36A Speed 166/133 MHz 166/133 MHz 166/133 MHz 166/133 MHz 166/133 MHz 166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/10 ns 166/133 MHz 166/133 MHz 166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/ ...
Page 3
... DQd2 22 DQd3 23 DQd4 24 25 DQd5 V 26 SSQ V 27 DDQ DQd6 28 29 DQd7 DQPd/NC 30 11/8/04, v. 1.1 ® TQFP 14x20mm Note: Pins 1, 30 and 80 are NC for ×32 Alliance Semiconductor AS7C33256NTF32A AS7C33256NTF36A 80 DQPb/NC 79 DQb7 78 DQb6 77 V DDQ 76 V SSQ 75 DQb5 74 DQb4 73 DQb3 72 DQb2 71 V SSQ ...
Page 4
... R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device operations, including burst, can be stalled using the CEN=1, the clock enable input. The AS7C33256NTF32A and AS7C33256NTF36A operate with a 3.3V ± 5% power supply for the device core (V separate power supply (V ) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin 14× ...
Page 5
... Starting Address First increment Second increment Third increment Alliance Semiconductor AS7C33256NTF32A AS7C33256NTF36A Linear Burst Order LBO ...
Page 6
... Next Current enables WRITEs to byte “b” (DQb pins/balls); Alliance Semiconductor AS7C33256NTF32A AS7C33256NTF36A Operation DESELECT Cycle High-Z DESELECT Cycle High-Z DESELECT Cycle High-Z CONTINUE DESELECT Cycle High-Z READ Cycle (Begin Burst) READ Cycle (Continue Burst) ...
Page 7
... OUT T stg T bias Symbol Min V 3.135 DD V 3.135 DDQ Vss 0 Symbol Min V 3.135 DD V 2.375 DDQ Vss 0 Alliance Semiconductor AS7C33256NTF32A AS7C33256NTF36A Burst Dsel Burst Burst Min Max Unit –0.5 +4.6 –0 0.5 DD –0 0.5 DDQ – 1.8 W – –65 +150 o –65 ...
Page 8
... OUT ≤ 0.2V or > V All V – 0.2V, Deselected < Max Deselected < 0.2V, ≤ 0.2V or ≥ V all ≥ V Deselected Max ≤ ≥ V all Alliance Semiconductor AS7C33256NTF32A AS7C33256NTF36A Min Max -2 2 < OUT DDQ * +0.3 DDQ ** -0.3 ...
Page 9
... DH t 0 0.5 - 0.5 CSH t 2.0 - 2.0 CENS t 0.5 - 0.5 CENH t 2.0 - 2.0 ADVS t 0.5 - 0.5 ADVH Conditions Symbol ZZ > SB2 t PDS t PUS t ZZI t RZZI Alliance Semiconductor AS7C33256NTF32A AS7C33256NTF36A –85 –10 Unit Notes – 12 – ns 8.5 – 4.0 – 4.0 ns – 2.5 – ns 2,3,4 – 2.5 – – 0 – ns 2,3,4 4.0 – 4.0 ns 2,3,4 5.0 – 5.0 ns 2,3,4 – 0 – ns – ...
Page 10
... Falling input HZOE Q(A2) Q(A2Y‘01) Q(A2Y‘10) BURST READ BURST BURST READ Q(A2) READ READ Q(A2Ý11) Q(A2Ý01) Q(A2Ý10) Alliance Semiconductor AS7C33256NTF32A AS7C33256NTF36A Undefined t CYC A3 Q(A2Y‘11) Q(A3) Q(A3Y‘01) STALL READ BURST Q(A3) READ Q(A3Ý01 ...
Page 11
... Din t HZOE Dout Q(n-1) DSEL WRITE Command D(A1) 11/8/04, v. 1.1 ® D(A2) D(A2Y‘01) D(A2Y‘10) BURST BURST BURST WRITE WRITE WRITE D(A2) WRITE D(A2Ý10) D(A2Ý11) D(A2Ý01) Alliance Semiconductor AS7C33256NTF32A AS7C33256NTF36A t CYC D(A3) D(A2Y‘11) D(A3Y‘01) STALL WRITE BURST D(A3) WRITE D(A3Ý01 ...
Page 12
... Note: Ý = XOR when LBO = high/no connect. Ý = ADD when LBO = low. 11/8/04, v. 1.1 ® HZOE LZC OH D(A2) Q(A3) Q(A4) D(A2Ý01) BURST BURST READ READ WRITE READ Q(A3) Q(A4) D(A2Ý01) Q(A4Ý01) Alliance Semiconductor AS7C33256NTF32A AS7C33256NTF36A t CYC HZC D(A5) Q(A6) D(A7) Q(A4Ý01) t LZOE WRITE READ WRITE DSEL D(A5) Q(A6) D(A7 ...
Page 13
... Command Q(A1) Q(A1 Ý Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low low. 11/8/04, v. 1.1 ® Q(A1Ý10) Q(A1Ý01) STALL DSEL BURST BURST 01) Q(A1 10) DSEL Ý Alliance Semiconductor AS7C33256NTF32A AS7C33256NTF36A A2 A3 D(A2) BURST WRITE WRITE BURST NOP NOP D(A2) D(A2 10) Ý D(A2 01) D(A3) Ý ...
Page 14
... Timing waveform of snooze mode CLK ZZ setup cycle ZZ t ZZI I supply I SB2 All inputs Deselect or Read Only (except ZZ) Dout 11/8/04, v. 1.1 ® t PUS ZZ recovery cycle t RZZI Deselect or Read Only High-Z Alliance Semiconductor AS7C33256NTF32A AS7C33256NTF36A Normal operation Cycle ...
Page 15
... D V =1.5V out L 30 pF* Figure B: Output load (A) at any given temperature and voltage. LZC measured as low below VIL Alliance Semiconductor AS7C33256NTF32A AS7C33256NTF36A Thevenin equivalent: +3.3V for 3.3V I/O; /+2.5V for 2.5V I/O 319Ω/1667Ω D OUT 5 pF* 353Ω/1538Ω GND *including scope and jig capacitance Figure C: Output load( Figure C ...
Page 16
... Package Dimensions 100-pin quad flat pack (TQFP) TQFP Min Max A1 0.05 0.15 A2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 D 13.80 14.20 E 19.80 20.20 e 0.65 nominal c Hd 15.80 16.20 He 21.80 22.20 L 0.45 0.75 L1 1.00 nominal α 0° 7° Dimensions in millimeters 11/8/04, v. 1.1 ® α Alliance Semiconductor AS7C33256NTF32A AS7C33256NTF36A ...
Page 17
... AS7C33256NTF32A-75TQC TQFP x32 AS7C33256NTF32A-75TQI TQFP x36 AS7C33256NTF36A-75TQC TQFP x36 AS7C33256NTF36A-75TQI Note: Add suffix ‘N’ above part numbers for Lead Free Parts (Ex. AS7C33256NTF32A-85TQCN) Part numbering guide AS7C 33 256 1.Alliance Semiconductor SRAM prefix 2.Operating voltage 3.3V 3.Organization: 256 = 256 K 4.NTF = No Turn-around Delay, Flowthrough mode 5.Organization x32 ...
Page 18
... Alliance products in such life- supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. AS7C33256NTF32A AS7C33256NTF36A ® Copyright © Alliance Semiconductor All Rights Reserved Part Number:AS7C33256NTF32A AS7C33256NTF36A Document Version: v. 1.1 ...