AS7C33256NTF32A ALSC [Alliance Semiconductor Corporation], AS7C33256NTF32A Datasheet - Page 5

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AS7C33256NTF32A

Manufacturer Part Number
AS7C33256NTF32A
Description
3.3V 256K x 2/36 Flowthrough Synchronous SRAM with NTD
Manufacturer
ALSC [Alliance Semiconductor Corporation]
Datasheet
Signal descriptions
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time t
become disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successful
complete. Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. similarly,
when exiting SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of
SNOOZE MODE.
Burst Order
Signal
CLK
CEN
A, A0, A1
DQ[a,b,c,d]
CE0, CE1,
CE2
ADV/LD
R/W
BW[a,b,c,d]
OE
LBO
ZZ
NC
11/8/04, v. 1.1
Second increment
Starting Address
Third increment
First increment
Interleaved Burst Order LBO=1
I/O Properties Description
I/O
I
I
I
I
I
I
I
I
I
I
-
CLOCK
ASYNC
ASYNC
STATIC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
-
A1 A0 A1 A0 A1 A0 A1 A0
0 0
0 1
1 0
1 1
Clock. All inputs except OE, LBO, and ZZ are synchronous to this clock.
Clock enable. When de-asserted high, the clock input signal is masked.
Address. Sampled when all chip enables are active and ADV/LD is asserted.
Data. Driven as output when the chip is enabled and OE is active.
Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted.
Are ignored when ADV/LD is high.
Advance or Load. When sampled high, the internal burst address counter will increment in
the order defined by the LBO input value. (refer to table on page 2) When low, a new
address is loaded.
A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE
operation. Is ignored when ADV/LD is high.
Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.
Asynchronous output enable. I/O pins are not driven when OE is inactive.
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
No connects. Note that pin 84 will be used for future address expansion to 16Mb density.
Selects Burst mode. When tied to V
order. When driven Low, device follows linear Burst order. This signal is internally pulled
High.
0 1
0 0
1 1
1 0
1 0
1 1
0 0
0 1
Alliance Semiconductor
1 1
1 0
0 1
0 0
ZZI
®
DD
Second increment
is met. After entering SNOOZE MODE, all inputs except ZZ
Starting Address
Third increment
First increment
or left floating, device follows Interleaved Burst
Linear Burst Order LBO=0
A1 A0 A1 A0 A1 A0 A1 A0
0 0
0 1
1 0
1 1
AS7C33256NTF32A
AS7C33256NTF36A
0 1
1 0
1 1
0 0
1 0
1 1
0 0
0 1
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1 1
0 0
0 1
1 0

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