EVAL-AD1934EB AD [Analog Devices], EVAL-AD1934EB Datasheet - Page 16

• Manufacturer Part Number: EVAL-AD1934EB
• Description: 8-Channel DAC with PLL, 192 kHz, 24 Bits
• Manufacturer: AD [Analog Devices]

AD1934
DAISY-CHAIN MODE
The AD1934 also allows a daisy-chain configuration to expand
the system 16 DACs (see Figure 12). In this mode, the DBCLK
frequency is 512 f
stream belong to the first AD1934 in the chain and the last eight
slots belong to the second AD1934. The second AD1934 is the
device attached to the DSP TDM port.
To accommodate 16 channels at a 96 kHz sample rate, the
AD1934 can be configured into a dual-line, DAC TDM mode,
as shown in Figure 13. This mode allows a slower DBCLK than
normally required by the one-line TDM mode.
Again, the first four channels of each TDM input belong to the
first AD1934 in the chain and the last four channels belong to
the second AD1934.
Figure 13. Dual-Line, DAC TDM Mode (Applicable to 96 kHz Sample Rate, 16-Channel, Two AD1934 Daisy Chain); DSDATA3 and DSDATA4 Are the Daisy Chain
OF THE SECOND AD1934
OF THE SECOND AD1934
TO THE FIRST AD1934
DSDATA2 (TDM_OUT)
DSDATA1 (TDM_IN)
THIS IS THE TDM
DSDATA1
DSDATA2
DSDATA3
DSDATA4
DLRCLK
DBCLK
(OUT)
(OUT)
(IN)
(IN)
AD1934
DLRCLK
FIRST
Figure 12. Single-Line DAC TDM Daisy-Chain Mode (Applicable to 48 kHz Sample Rate, 16-Channel, Two AD1934 Daisy Chain)
DBCLK
S
. The first eight slots of the DAC TDM data
AD1934
FIRST
DAC L1
DAC L3
8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN
DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4 DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4
SECOND
AD1934
MSB
8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN
SECOND
AD1934
DAC R1
DAC R3
32 BITS
DSP
8 UNUSED SLOTS
DSP
DAC L2
DAC L4
DAC R2
DAC R4
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DAC L1
DAC L1
DAC L3
DAC L3
8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN
The dual-line, DAC TDM mode can also be used to send data at
a 192 kHz sample rate into the AD1934, as shown in Figure 14.
The I/O pins of the serial ports are defined according to the
serial mode selected. See Table 13 for a detailed description of
the function of each pin. See Figure 18 for a typical AD1934
configuration with two external stereo DACs. Figure 15 and
Figure 16 show the serial mode formats. For maximum
flexibility, the polarity of LRCLK and BCLK are programmable.
In these figures, all of the clocks are shown with their normal
polarity. The default mode is I
DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4
8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN
MSB
32 BITS
DAC R1
DAC R1
DAC R3
DAC R3
DAC L2
DAC L2
DAC L4
DAC L4
2
S.
DAC R2
DAC R2
DAC R4
DAC R4