EVAL-AD7327CB AD [Analog Devices], EVAL-AD7327CB Datasheet - Page 32

• Manufacturer Part Number: EVAL-AD7327CB
• Description: 500 kSPS, 8-Channel, Software-Selectable, True Bipolar Input, 12-Bit Plus Sign ADC
• Manufacturer: AD [Analog Devices]

AD7327
SERIAL INTERFACE
Figure 53 shows the timing diagram for the serial interface of
the AD7327. The serial clock applied to the SCLK pin provides
the conversion clock and controls the transfer of information to
and from the AD7327 during a conversion.
The CS signal initiates the data transfer and the conversion
process. The falling edge of CS puts the track-and-hold into
hold mode and takes the bus out of three-state. Then the analog
input signal is sampled. Once the conversion is initiated, it
requires 16 SCLK cycles to complete.
The track-and-hold goes back into track mode on the 14
rising edge. On the 16
returns to three-state. If the rising edge of CS occurs before
16 SCLK cycles have elapsed, the conversion is terminated,
and the DOUT line returns to three-state. Depending on where
the CS signal is brought high, the addressed register may be
updated.
DOUT
SCLK
DIN
CS
THREE-
STATE
th
SCLK falling edge, the DOUT line
WRITE
ADD2
t
2
1
3 IDENTIFICATION BITS
t
ADD1
3
t
SEL1
9
REG
2
ADD0
SEL2
REG
Figure 53. Serial Interface Timing Diagram (Control Register Write)
3
SIGN
MSB
4
DB11
t
t
6
4
t
CONVERT
th
t
10
5
SCLK
t
DB10
7
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Data is clocked into the AD7327 on the SCLK falling edge. The
three MSBs on the DIN line are decoded to select which register
is addressed. The control register is a 12-bit register. If the
control register is addressed by the three MSBs, the data on the
DIN line is loaded into the control on the 15
edge. If the sequence register or either of the range registers is
addressed, the data on the DIN line is loaded into the addressed
register on the 11
Conversion data is clocked out of the AD7327 on each SCLK
falling edge. Data on the DOUT line consists of three channel
identifier bits, a sign bit, and a 12-bit conversion result. The
channel identifier bits are used to indicate which channel
corresponds to the conversion result. The ADD2 bit is clocked
out on the CS falling edge, and the ADD1 bit is clocked out on
the first SCLK falling edge.
DB2
14
t
5
DB1
LSB
15
DB0
DON’T
CARE
th
16
SCLK falling edge.
THREE-STATE
t
8
t
QUIET
t
1
th
SCLK falling