RFPIC12F675 MICROCHIP [Microchip Technology], RFPIC12F675 Datasheet - Page 62

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RFPIC12F675

Manufacturer Part Number
RFPIC12F675
Description
20-Pin FLASH-Based 8-Bit CMOS Microcontroller with UHF ASK/FSK Transmitter
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet

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rfPIC12F675
10.3.1
The rfPIC12F675 devices have a noise filter in the
MCLR Reset path. The filter will detect and ignore
small pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
The behavior of the ESD protection on the MCLR pin
has been altered from previous devices of this family.
Voltages applied to the pin that exceed its specification
can result in both MCLR Resets and excessive current
beyond the device specification during the ESD event.
For this reason, Microchip recommends that the MCLR
pin no longer be tied directly to V
network, as shown in Figure 10-5, is suggested.
An internal MCLR option is enabled by setting the
MCLRE bit in the configuration word. When enabled,
MCLR is internally tied to V
option is available for the MCLR pin.
FIGURE 10-5:
10.3.2
The on-chip POR circuit holds the chip in RESET until
V
operation. To take advantage of the POR, simply tie the
MCLR pin through a resistor to V
external RC components usually needed to create
Power-on Reset. A maximum rise time for V
required. See Electrical Specifications for details (see
Section 13.0).
When the device starts normal operation (exits the
RESET condition), device operating parameters (i.e.,
voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in RESET until the operating
conditions are met.
For additional information, refer to Application Note
AN607 “Power-up Trouble Shooting”.
DS70091A-page 60
DD
Note:
has reached a high enough level for proper
V
DD
R1
1 kΩ (or greater)
C1
0.1
(optional, not critical)
The POR circuit does not produce an
internal RESET when V
MCLR
POWER-ON RESET (POR)
µ
f
RECOMMENDED
CIRCUIT
DD
DD
DD
. No internal pull-up
MCLR
PIC12F629/675
DD
. The use of an RC
. This will eliminate
declines.
MCLR
DD
Preliminary
is
10.3.3
The Power-up Timer provides a fixed 72 ms (nominal)
time-out on power-up only, from POR or Brown-out
Detect. The Power-up Timer operates on an internal
RC oscillator. The chip is kept in RESET as long as
PWRT is active. The PWRT delay allows the V
rise to an acceptable level. A configuration bit, PWRTE
can disable (if set) or enable (if cleared or
programmed) the Power-up Timer. The Power-up
Timer should always be enabled when Brown-out
Detect is enabled.
The Power-up Time delay will vary from chip to chip
and due to:
• V
• Temperature variation
• Process variation
See DC parameters for details (Section 13.0).
10.3.4
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal
oscillator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
DD
variation
POWER-UP TIMER (PWRT)
OSCILLATOR START-UP TIMER
(OST)
 2003 Microchip Technology Inc.
DD
to

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