X28HC64S-12 Xicor, X28HC64S-12 Datasheet

X28HC64S-12

Manufacturer Part Number

X28HC64S-12

Description

Manufacturer

Xicor

Datasheet

1.X28HC64S-12.pdf (24 pages)

Specifications of X28HC64S-12

Case

SMD28

Date_code

06+

Current page: 1 of 24
Download datasheet (104Kb)

X28HC64

64K

FEATURES

•

PIN CONFIGURATIONS

3857-3.0 2/24/99 T1/C0/D0 EW

V SS

I/O 0

I/O 1

I/O 2

A 12

A 7

A 6

A 5

A 4

A 3

A 2

A 1

A 0

70ns Access Time

Simple Byte and Page Write

—Single 5V Supply

—Self-Timed

Low Power CMOS

—40 mA Active Current Max.

—200 µA Standby Current Max.

Fast Write Cycle Times

—64 Byte Page Write Operation

—Byte or Page Write Cycle: 2ms Typical

—Complete Memory Rewrite: 0.25 sec. Typical

—Effective Byte Write Cycle Time: 32µs Typical

Software Data Protection

End of Write Detection

—DATA Polling

—Toggle Bit

—No External High Voltages or V

—No Erase Before Write

—No Complex Programming Algorithms

—No Overerase Problem

Circuits

PLASTIC DIP

FLAT PACK

X28HC64

CERDIP

SOIC

3857 FHD F02.1

V CC

A 8

A 9

A 11

A 10

I/O 7

I/O 6

I/O 5

I/0 4

I/O 3

I/O 0

A 6

A 5

A 4

A 3

A 2

A 1

A 0

5 Volt, Byte Alterable E

14 15 16 17 18 19 20

X28HC64

PLCC

LCC

Control

1 32 31 30

X28HC64

3857 FHD F03

A 8

A 9

A 11

A 10

I/O 7

I/O 6

•

DESCRIPTION

The X28HC64 is an 8K x 8 E

Xicor’s proprietary, high performance, floating gate

CMOS technology. Like all Xicor programmable non-

volatile memories the X28HC64 is a 5V only device. The

X28HC64 features the JEDEC approved pinout for byte-

wide memories, compatible with industry standard RAMs.

The X28HC64 supports a 64-byte page write operation,

effectively providing a 32µs/byte write cycle and enabling

the entire memory to be typically written in 0.25 seconds.

The X28HC64 also features DATA Polling and Toggle Bit

Polling, two methods providing early end of write detec-

tion. In addition, the X28HC64 includes a user-optional

software data protection mode that further enhances

Xicor’s hardware write protect capability.

Xicor E

tions requiring extended endurance. Inherent data re-

tention is greater than 100 years.

High Reliability

—Endurance: 1 Million Cycles

—Data Retention: 100 Years

JEDEC Approved Byte-Wide Pinout

V SS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

A 10

A 2

A 1

A 0

PROMs are designed and tested for applica-

PROM

I/O 1

I/O 0

A 1

A 3

A 5

A 6

I/O 2

A 0

A 2

A 4

A 12

A 7

BOTTOM VIEW

X28HC64

TSOP

Characteristics subject to change without notice

X28HC64

PGA

I/O 3

V SS

V CC

PROM, fabricated with

I/O 5

I/O 4

A 9

I/O 6

I/O 7

A 10

A 11

A 8

8K x 8 Bit

3857 FHD F04

3857 ILL F22

A 3

A 4

A 5

A 6

A 7

A 12

V CC

A 8

A 9

A 11

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