ISPLSI103260LJ Lattice Semiconductor Corp., ISPLSI103260LJ Datasheet

ISPLSI103260LJ

Manufacturer Part Number

ISPLSI103260LJ

Description

PLCC84

Manufacturer

Lattice Semiconductor Corp.

Datasheet

1.ISPLSI103260LJ.pdf (16 pages)

Specifications of ISPLSI103260LJ

Date_code

04+

Current page: 1 of 16
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• HIGH-DENSITY PROGRAMMABLE LOGIC

• HIGH PERFORMANCE E

• IN-SYSTEM PROGRAMMABLE

• COMBINES EASE OF USE AND THE FAST SYSTEM

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

1032_07

Features

— High Speed Global Interconnect

— 6000 PLD Gates

— 64 I/O Pins, Eight Dedicated Inputs

— 192 Registers

— Wide Input Gating for Fast Counters, State

— Small Logic Block Size for Fast Random Logic

— Security Cell Prevents Unauthorized Copying

—

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile E

— 100% Tested

— In-System Programmable™ (ISP™) 5-Volt Only

— Increased Manufacturing Yields, Reduced Time-to-

— Reprogram Soldered Devices for Faster Prototyping

SPEED OF PLDs WITH THE DENSITY AND FLEX-

— Four Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

— PC and UNIX Platforms

IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Market, and Improved Product Quality

Machines, Address Decoders, etc.

Logic and Structured Designs

Interconnectivity

Tools, Timing Simulator and ispANALYZER™

max = 90 MHz Maximum Operating Frequency

max = 60 MHz for Industrial and Military/883 Devices

pd = 12 ns Propagation Delay

CMOS Technology

CMOS

TECHNOLOGY

In-System Programmable High Density PLD

The ispLSI 1032 is a High-Density Programmable Logic

Device containing 192 Registers, 64 Universal I/O pins,

eight Dedicated Input pins, four Dedicated Clock Input

pins and a Global Routing Pool (GRP). The GRP pro-

vides complete interconnectivity between all of these

elements. The ispLSI 1032 features 5-Volt in-system

programming and in-system diagnostic capabilities. It is

the first device which offers non-volatile reprogrammability

of the logic, as well as the interconnect to provide truly

reconfigurable systems.

The basic unit of logic on the ispLSI 1032 device is the

Generic Logic Block (GLB). The GLBs are labeled A0, A1

.. D7 (see figure 1). There are a total of 32 GLBs in the

ispLSI 1032 device. Each GLB has 18 inputs, a program-

mable AND/OR/XOR array, and four outputs which can

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

other GLB on the device.

Functional Block Diagram

Description

D7 D6 D5 D4 D3 D2 D1 D0

B0 B1 B2 B3 B4 B5 B6 B7

Global Routing Pool (GRP)

Output Routing Pool

ispLSI

Logic

Array

D Q

GLB

1032

March 1999

CLK

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