CY7C4261V-15JI Cypress Semiconductor Corporation., CY7C4261V-15JI Datasheet

CY7C4261V-15JI

Manufacturer Part Number

CY7C4261V-15JI

Description

Manufacturer

Cypress Semiconductor Corporation.

Datasheets

1.CY7C4281V-25JC.pdf (16 pages)

2.CY7C4281V-25JC.pdf (16 pages)

3.CY7C4261V-15JI.pdf (16 pages)

Specifications of CY7C4261V-15JI

Package

PLCC

Date_code

05+

Current page: 1 of 16
Download datasheet (453Kb)

Cypress Semiconductor Corporation

Document #: 38-06013 Rev. *B

CY7C4281V/CY7C4291V CY7C4261V/CY7C4271V16K/32K/64K/128K x 9 Low-Voltage Deep Sync™ FIFOs

Features

• 3.3V operation for low power consumption and easy

• High-speed, low-power, first-in first-out (FIFO)

• 16K × 9 (CY7C4261V)

• 32K × 9 (CY7C4271V)

• 64K × 9 (CY7C4281V)

• 128K × 9 (CY7C4291V)

• 0.35-micron CMOS for optimum speed/power

• High-speed 100-MHz operation (10-ns read/write cycle

• Low power

• Fully asynchronous and simultaneous read and write

• Empty, Full, and programmable Almost Empty and

• Output Enable (OE) pin

• Independent read and write enable pins

• Supports free-running 50% duty cycle clock inputs

• Width- Expansion capability

• Pin-compatible 3.3V solutions for CY7C4261/71/81/91

integration into low-voltage systems

memories

times)

— I

operation

Almost Full status flags

LogicBlock Diagram

WCLK

= 25 mA

= 4 mA

WEN1

CONTROL

POINTER

WRITE

16K/32K/64K/128K x 9 Low-Voltage Deep Sync™ FIFOs

RESET

WRITE

LOGIC

WEN2/LD

OUTPUT REGISTER

THREE-STATE

RAM Array

Dual Port

16K/32K

64K/128K

INPUT

0–8

x 9

0–8

•

3901 North First Street

RCLK

PROGRAM

CONTROL

POINTER

FLAG

READ

FLAG

LOGIC

REN1 REN2

READ

Functional Description

The CY7C4261/71/81/91V are high-speed, low-power FIFO

memories with clocked read and write interfaces. All are nine

bits wide. The CY7C4261/71/81/91V are pin-compatible to the

CY7C42x1V Synchronous FIFO family. Programmable

features include Almost Full/Almost Empty flags. These FIFOs

provide solutions for a wide variety of data buffering needs,

including high-speed data acquisition, multiprocessor inter-

faces, and communications buffering.

These FIFOs have 9-bit input and output ports that are

controlled by separate clock and enable signals. The input port

is controlled by a free-running clock (WCLK) and two

write-enable pins (WEN1, WEN2/LD).

When WEN1 is LOW and WEN2/LD is HIGH, data is written

into the FIFO on the rising edge of the WCLK signal. While

WEN1 and WEN2/LD are held active, data is continually

written into the FIFO on each WCLK cycle. The output port is

controlled in a similar manner by a free-running read clock

(RCLK) and two read enable pins (REN1, REN2). In addition,

the CY7C4261/71/81/91V has an output enable pin (OE). The

read (RCLK) and write (WCLK) clocks may be tied together for

single-clock operation or the two clocks may be run indepen-

dently for asynchronous read/write applications. Clock

frequencies up to 100 MHz are achievable. Depth expansion

is possible using one enable input for system control, while the

other enable is controlled by expansion logic to direct the flow

of data.

• Pin-compatible density upgrade to CY7C42X1V family

• Pb-Free Packages Available

PAE

PAF

•

San Jose

Pin Configuration

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

REN1

RCLK

REN2

GND

PAE

PAF

CA 95134

14 15 16 17 18 19 20

4 3 2 1

CY7C4261V

CY7C4271V

CY7C4281V

CY7C4291V

Top View

PLCC

Revised August 2, 2005

•

31 30

408-943-2600

WEN1

WCLK

WEN2/LD

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