CY7C1514V18-300BZXC Cypress Semiconductor Corporation., CY7C1514V18-300BZXC Datasheet
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CY7C1514V18-300BZXC
Manufacturer Part Number
CY7C1514V18-300BZXC
Description
Manufacturer
Cypress Semiconductor Corporation.
Specifications of CY7C1514V18-300BZXC
Package
BGA
Date_code
09+
Cypress Semiconductor Corporation
Document #: 38-05489 Rev. *D
Features
Configurations
CY7C1510V18 – 8M x 8
CY7C1525V18 – 8M x 9
CY7C1512V18 – 4M x 18
CY7C1514V18 – 2M x 36
Selection Guide
Maximum Operating Frequency
Maximum Operating Current
• Separate Independent Read and Write Data Ports
• 250-MHz clock for high bandwidth
• 2-Word Burst on all accesses
• Double Data Rate (DDR) interfaces on both Read and
• Two input clocks (K and K) for precise DDR timing
• Two input clocks for output data (C and C) to minimize
• Echo clocks (CQ and CQ) simplify data capture in high
• Single multiplexed address input bus latches address
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• Available in x8, x9, x18, and x36 configurations
• Full data coherency, providing most current data
• Core V
• Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
• Offered in lead-free and non-lead free packages
• Variable drive HSTL output buffers
• JTAG 1149.1 compatible test access port
• Delay Lock Loop (DLL) for accurate data placement
— Supports concurrent transactions
Write ports (data transferred at 500 MHz) @ 250 MHz
— SRAM uses rising edges only
clock-skew and flight-time mismatches
speed systems
inputs for both Read and Write ports
DD
= 1.8V (±0.1V); I/O V
DDQ
= 1.4V to V
•
198 Champion Court
72-Mbit QDR-II™ SRAM 2-Word Burst
DD
250 MHz
250
950
Functional Description
The CY7C1510V18, CY7C1525V18, CY7C1512V18, and
CY7C1514V18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR-II architecture. QDR-II architecture
consists of two separate ports to access the memory array.
The Read port has dedicated Data Outputs to support Read
operations and the Write Port has dedicated Data Inputs to
support Write operations. QDR-II architecture has separate
data inputs and data outputs to completely eliminate the need
to “turn-around” the data bus required with common I/O
devices. Access to each port is accomplished through a
common address bus. The Read address is latched on the
rising edge of the K clock and the Write address is latched on
the rising edge of the K clock. Accesses to the QDR-II Read
and Write ports are completely independent of one another. In
order to maximize data throughput, both Read and Write ports
are equipped with Double Data Rate (DDR) interfaces. Each
address location is associated with two 8-bit words
(CY7C1510V18) or 9-bit words (CY7C1525V18) or 18-bit
words (CY7C1512V18) or 36-bit words (CY7C1514V18) that
burst sequentially into or out of the device. Since data can be
transferred into and out of the device on every rising edge of
both input clocks (K and K and C and C), memory bandwidth
is maximized while simplifying system design by eliminating
bus “turn-arounds.”
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
•
200 MHz
San Jose
200
850
,
CA 95134-1709
167 MHz
Revised May 31, 2006
167
800
CY7C1510V18
CY7C1525V18
CY7C1512V18
CY7C1514V18
Architecture
•
408-943-2600
MHz
Unit
mA
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