CY7C1515V18-300BZC Cypress Semiconductor Corporation., CY7C1515V18-300BZC Datasheet

CY7C1515V18-300BZC

Manufacturer Part Number

CY7C1515V18-300BZC

Description

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.CY7C1515V18-300BZC.pdf (28 pages)

Specifications of CY7C1515V18-300BZC

Package

FBGA

Date_code

10+

Current page: 1 of 28
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Cypress Semiconductor Corporation

Document #: 38-05363 Rev. *D

Features

Configurations

CY7C1511V18 – 8M x 8

CY7C1526V18 – 8M x 9

CY7C1513V18 – 4M x 18

CY7C1515V18 – 2M x 36

Selection Guide

Maximum Operating Frequency

Maximum Operating Current

• Separate Independent Read and Write Data Ports

• 300-MHz Clock for High Bandwidth

• 4-Word Burst for reducing address bus frequency

• Double Data Rate (DDR) interfaces on both Read and

• Two input clocks (K and K) for precise DDR timing

• Two input clocks for output data (C and C) to minimize

• Echo clocks (CQ and CQ) simplify data capture in high

• Single multiplexed address input bus latches address

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• Available in x8, x9, x18, and x36 configurations

• Full data coherency providing most current data

• Core V

• Available in 165-ball FBGA package (15 x 17 x 1.4 mm)

• Offered in both lead-free and non-lead free packages

• Variable drive HSTL output buffers

• JTAG 1149.1 Compatible test access port

• Delay Lock Loop (DLL) for accurate data placement

— Supports concurrent transactions

Write Ports (data transferred at 600 MHz) at 300 MHz

— SRAM uses rising edges only

clock-skew and flight-time mismatches

speed systems

inputs for both Read and Write ports

= 1.8 (±0.1V); I/O V

DDQ

= 1.4V to V

•

300 MHz

300

950

198 Champion Court

72-Mbit QDR™- II SRAM 4-Word Burst

278 MHz

900

278

Functional Description

The CY7C1511V18, CY7C1526V18, CY7C1513V18, and

CY7C1515V18 are 1.8V Synchronous Pipelined SRAMs,

equipped with QDR-II architecture. QDR-II architecture

consists of two separate ports to access the memory array.

The Read port has dedicated Data Outputs to support Read

operations and the Write Port has dedicated Data Inputs to

support Write operations. QDR-II architecture has separate

data inputs and data outputs to completely eliminate the need

to “turn-around” the data bus required with common I/O

devices. Access to each port is accomplished through a

common address bus. Addresses for Read and Write

addresses are latched on alternate rising edges of the input

(K) clock. Accesses to the QDR-II Read and Write ports are

completely independent of one another. In order to maximize

data throughput, both Read and Write ports are equipped with

Double Data Rate (DDR) interfaces. Each address location is

associated with four 8-bit words (CY7C1511V18) or 9-bit

words (CY7C1526V18) or 18-bit words (CY7C1513V18) or

36-bit words (CY7C1515V18) that burst sequentially into or

out of the device. Since data can be transferred into and out

of the device on every rising edge of both input clocks (K and

K and C and C), memory bandwidth is maximized while simpli-

fying system design by eliminating bus “turn-arounds”.

Depth expansion is accomplished with Port Selects for each

port. Port selects allow each port to operate independently.

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

•

250 MHz

250

850

San Jose

CA 95134-1709

200 MHz

200

750

Revised May 31, 2006

167 MHz

CY7C1526V18

CY7C1513V18

CY7C1515V18

Architecture

CY7C1511V18

167

700

•

408-943-2600

Unit

MHz

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