74LVC573ATTR STMicroelectronics, 74LVC573ATTR Datasheet

IC LATCH OCTAL D LV 20-TSSOP

74LVC573ATTR

Manufacturer Part Number
74LVC573ATTR
Description
IC LATCH OCTAL D LV 20-TSSOP
Manufacturer
STMicroelectronics
Series
74LVCr
Datasheet

Specifications of 74LVC573ATTR

Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
1.65 V ~ 3.6 V
Independent Circuits
1
Delay Time - Propagation
1ns
Current - Output High, Low
24mA, 24mA
Operating Temperature
-55°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-7108-2
74LVC573ATTR

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DESCRIPTION
The 74LVC573A is a low voltage CMOS OCTAL
D-TYPE LATCH fabricated with sub-micron silicon
gate and double-layer metal wiring C
technology. It is ideal for 1.65 to 3.6 V
operations and low power and low noise
applications.
These 8 bit D-Type latch are controlled by a latch
enable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q
Figure 1: Pin Connection And IEC Logic Symbols
July 2004
5V TOLERANT INPUTS
HIGH SPEED: t
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
t
OPERATING VOLTAGE RANGE:
V
Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573
LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
PLH
OH
CC
| = I
(OPR) = 1.65V to 3.6V (1.2V Data
t
PHL
OL
= 24mA (MIN) at V
PD
= 6.8ns (MAX.) at V
CC
= 3V
CC
2
MOS
= 3V
CC
Table 1: Order Codes
outputs will follow the data input precisely or
inversely. When the LE is taken low, the Q outputs
will be latched precisely or inversely at the logic
level of D input data. While the (OE) input is low,
the 8 outputs will be in a normal logic state (high or
low logic level) and while high level the outputs will
be in a high impedance state.
This device is designed to interface directly High
Speed CMOS systems with TTL and NMOS
components. It has more speed performance at
3.3V than 5V AC/ACT family, combined with a
lower power consumption.
All inputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
PACKAGE
TSSOP
OCTAL D-TYPE LATCH
SOP
HIGH PERFORMANCE
SOP
74LVC573A
Rev. 3
74LVC573AMTR
74LVC573ATTR
TSSOP
T & R
1/13

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74LVC573ATTR Summary of contents

Page 1

... AC/ACT family, combined with a lower power consumption. All inputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. 74LVC573A OCTAL D-TYPE LATCH HIGH PERFORMANCE SOP TSSOP PACKAGE T & R SOP 74LVC573AMTR TSSOP 74LVC573ATTR Rev. 3 1/13 ...

Page 2

Figure 2: Input And Output Equivalent Circuit Table 2: Pin Description PIN N° SYMBOL NAME AND FUNCTION State Output Enable Input (Active LOW Data Inputs ...

Page 3

Table 5: Recommended Operating Conditions Symbol V Supply Voltage (note Input Voltage I V Output Voltage ( Output Voltage (High or Low State High or Low Level Output Current (V ...

Page 4

Table 7: Dynamic Switching Characteristics Symbol Parameter V Dynamic Low Level Quiet OLP Output (note 1) V OLV 1) Number of output defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The ...

Page 5

Table 9: Capacitive Characteristics Symbol Parameter C Input Capacitance IN C Power Dissipation Capacitance PD (note defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without PD ...

Page 6

Figure 4: Waveform - Propagation Delay, Setup And Hold Times (f=1MHz; 50% duty cycle) Figure 5: Waveform - Output Enable And Disable Times (f=1MHz; 50% duty cycle) 6/13 ...

Page 7

Figure 6: Waveform - Propagation Delay Time (f=1MHz; 50% duty cycle) 74LVC573A 7/13 ...

Page 8

DIM. MIN. A 2.35 A1 0.1 B 0.33 C 0.23 D 12. 10.00 h 0.25 L 0.4 k 0° ddd 8/13 SO-20 MECHANICAL DATA mm. TYP MAX. 2.65 0.30 0.51 0.32 13.00 7.6 1.27 10.65 ...

Page 9

TSSOP20 MECHANICAL DATA DIM. MIN 0.05 A2 0.8 b 0.19 c 0.09 D 6.4 E 6 0˚ PIN 1 IDENTIFICATION 1 mm. TYP MAX. 1.2 0.15 1 1.05 ...

Page 10

DIM. MIN 12 10.8 Bo 13.2 Ko 3.1 Po 3.9 P 11.9 10/13 Tape & Reel SO-20 MECHANICAL DATA mm. TYP MAX. 330 13.2 30.4 11 13.4 3.3 4.1 12.1 inch ...

Page 11

Tape & Reel TSSOP20 MECHANICAL DATA DIM. MIN 12 6.8 Bo 6.9 Ko 1.7 Po 3.9 P 11.9 mm. TYP MAX. 330 13.2 0.504 0.795 2.362 22.4 7 0.268 7.1 0.272 1.9 ...

Page 12

Table 11: Revision History Date Revision 26-Jul-2004 3 12/13 Description of Changes Ordering Codes Revision - pag. 1. ...

Page 13

... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...

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