74ABT573CSJX Fairchild Semiconductor, 74ABT573CSJX Datasheet - Page 2
![no-image](/images/manufacturer_photos/0/2/252/fairchild_semiconductor_sml.jpg)
74ABT573CSJX
Manufacturer Part Number
74ABT573CSJX
Description
IC LATCH OCT D-TYPE 3ST 20SOP
Manufacturer
Fairchild Semiconductor
Series
74ABTr
Datasheet
1.74ABT573CSJX.pdf
(13 pages)
Specifications of 74ABT573CSJX
Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
4.5 V ~ 5.5 V
Independent Circuits
1
Delay Time - Propagation
2.7ns
Current - Output High, Low
32mA, 64mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
©1993 Fairchild Semiconductor Corporation
74ABT573 Rev. 1.5.0
Connection Diagram
Pin Descriptions
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
D
LE
OE
O
Pin Names
0
0
–D
–O
7
7
Data Inputs
Latch Enable Input (Active HIGH)
3-STATE Output Enable Input
(Active LOW)
3-STATE Latch Outputs
Descriptions
2
Functional Description
The ABT573 contains eight D-type latches with 3-STATE
output buffers. When the Latch Enable (LE) input is
HIGH, data on the D
condition the latches are transparent, i.e., a latch output
will change state each time its D input changes. When
LE is LOW the latches store the information that was
present on the D inputs a setup time preceding the
HIGH-to-LOW transition of LE. The 3-STATE buffers are
controlled by the Output Enable (OE) input. When OE is
LOW, the buffers are in the bi-state mode. When OE is
HIGH the buffers are in the high impedance mode but
this does not interfere with entering new data into the
latches.
Function Table
H
L
X
O
0
LOW Voltage Level
Immaterial
HIGH Voltage Level
OE
Value stored from previous clock cycle
H
L
L
L
Inputs
LE
H
H
X
L
n
inputs enters the latches. In this
D
H
X
X
L
Outputs
www.fairchildsemi.com
O
O
H
Z
L
0