ISPLSI5384VA-100LB208 Lattice Semiconductor Corp., ISPLSI5384VA-100LB208 Datasheet

ISPLSI5384VA-100LB208

Manufacturer Part Number

ISPLSI5384VA-100LB208

Description

Manufacturer

Lattice Semiconductor Corp.

Datasheets

1.ISPLSI5384VA-100LB208.pdf (28 pages)

2.ISPLSI5384VA-100LB208.pdf (31 pages)

3.ISPLSI5384VA-100LB208.pdf (31 pages)

Specifications of ISPLSI5384VA-100LB208

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• SuperWIDE HIGH-DENSITY IN-SYSTEM

• HIGH PERFORMANCE E

• IN-SYSTEM PROGRAMMABLE

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND

• ARCHITECTURE FEATURES

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

5384va_04

Features

PROGRAMMABLE LOGIC

— 3.3V Power Supply

— User Selectable 3.3V/2.5V I/O

— 18,000 PLD Gates / 384 Macrocells

— Up to 288 I/O Pins

— 384 Registers

— High-Speed Global Interconnect

— SuperWIDE 32 Generic Logic Block (GLB) Size for

— SuperWIDE Input Gating (68 Inputs) for Fast

— PCB Efficient Ball Grid Array (BGA) Package

— Interfaces with Standard 5V TTL Devices

—

— Enhanced

— TTL/3.3V/2.5V Compatible Input Thresholds and

— Electrically Erasable and Reprogrammable

— Non-Volatile

— Programmable Speed/Power Logic Path

— Increased Manufacturing Yields, Reduced Time-to-

— Reprogram Soldered Devices for Faster Debugging

3.3V IN-SYSTEM PROGRAMMABLE

— Enhanced Pin-Locking Architecture with Single-

— Wrap Around Product Term Sharing Array Supports

— Macrocells Support Concurrent Combinatorial and

— Macrocell Registers Feature Multiple Control

— Four Dedicated Clock Input Pins Plus Macrocell

— Slew and Skew Programmable I/O (SASPI/O™)

— Six Global Output Enable Terms, Two Global OE

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

Market, and Improved Product Quality

Optimum Performance

Counters, State Machines, Address Decoders, etc.

Options

Output Levels

Optimization

Level Global Routing Pool and SuperWIDE GLBs

up to 35 Product Terms Per Macrocell

Registered Functions

Options Including Set, Reset and Clock Enable

Product Term Clocks

Supports Programmable Bus Hold, Pull-up, Open

Drain and Slew and Skew Rate Options

Pins and One Product Term OE per Macrocell

max = 125 MHz Maximum Operating Frequency

pd = 7.5 ns Propagation Delay

su3 (CLK2/3) = 3.5ns

su2 = 7 ns,

CMOS

su3 (CLK0/1) = 4.5ns,

TECHNOLOGY

The ispLSI 5000V Family of In-System Programmable

High Density Logic Devices is based on Generic Logic

Blocks (GLBs) of 32 registered macrocells and a single

Global Routing Pool (GRP) structure interconnecting the

GLBs.

Outputs from the GLBs drive the Global Routing Pool

(GRP) between the GLBs. Switching resources are pro-

vided to allow signals in the Global Routing Pool to drive

any or all the GLBs in the device. This mechanism allows

fast, efficient connections across the entire device.

Each GLB contains 32 macrocells and a fully populated,

programmable AND-array with 160 logic product terms

and five extra control product terms. The GLB has 68

inputs from the Global Routing Pool which are available

in both true and complement form for every product term.

Functional Block Diagram

ispLSI 5000V Description

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

— PC and UNIX Platforms

Tools, Timing Simulator and ispANALYZER™

3.3V SuperWIDE™ High Density PLD

Logic Block

Generic

Input Bus

ispLSI

Global Routing Pool

In-System Programmable

Logic Block

Generic

Input Bus

(GRP)

5384VA

Logic Block

Generic

Input Bus

September 2000

Boundary

Interface

Scan

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