CY7C142-55DMB Cypress Semiconductor Corporation., CY7C142-55DMB Datasheet

CY7C142-55DMB

Manufacturer Part Number

CY7C142-55DMB

Description

Manufacturer

Cypress Semiconductor Corporation.

Datasheets

1.CY7C132-45DMB.pdf (18 pages)

2.CY7C132-45DMB.pdf (18 pages)

3.CY7C142-55DMB.pdf (18 pages)

Specifications of CY7C142-55DMB

Date_code

00+

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

CY7C142-55DMB

Manufacturer:

CYP

Quantity:

259

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Features

Notes:

Cypress Semiconductor Corporation

• True Dual-Ported memory cells which allow simulta-

• 2K x 8 organization

• 0.65-micron CMOS for optimum speed/power

• High-speed access: 15 ns

• Low operating power: I

• Fully asynchronous operation

• Automatic power-down

• Master CY7C132/CY7C136 easily expands data bus

• BUSY output flag on CY7C132/CY7C136; BUSY input

• INT flag for port-to-port communication (52-pin

• Available in 48-pin DIP (CY7C132/142), 52-pin PLCC and

• Pin-compatible and functionally equivalent to

neous reads of the same memory location

width to 16 or more bits using slave CY7C142/CY7C146

on CY7C142/CY7C146

PLCC/PQFP versions)

52-pin TQFP (CY7C136/146)

IDT7132/IDT7142

Logic Block Diagram

BUSY

CY7C132/CY7C136 (Master): BUSY is open drain output and requires pull-up resistor.

CY7C142/CY7C146 (Slave): BUSY is input.

Open drain outputs; pull-up resistor required.

INT

R/W

I/O

10L

[1]

[2]

DECODER

ADDRESS

R/W

CONTROL

= 90 mA (max.)

I/O

(7C132/7C136 ONLY)

(7C136/7C146 ONLY)

INTERRUPTLOGIC

ARBITRA TION

MEMORY

ARRAY

LOGIC

•

AND

3901 North First Street

CONTROL

I/O

DECODER

ADDRESS

R/W

Functional Description

The

high-speed CMOS 2K by 8 dual-port static RAMs. Two ports

are provided to permit independent access to any location in

memory. The CY7C132/ CY7C136 can be utilized as either a

standalone 8-bit dual-port static RAM or as a MASTER du-

al-port RAM in conjunction with the CY7C142/CY7C146

SLAVE dual-port device in systems requiring 16-bit or greater

word widths. It is the solution to applications requiring shared

or buffered data such as cache memory for DSP, bit-slice, or

multiprocessor designs.

Each port has independent control pins; chip enable (CE),

write enable (R/W), and output enable (OE). BUSY flags are

provided on each port. In addition, an interrupt flag (INT) is

provided on each port of the 52-pin PLCC version. BUSY sig-

nals that the port is trying to access the same location currently

being accessed by the other port. On the PLCC version, INT

is an interrupt flag indicating that data has been placed in a

unique location (7FF for the left port and 7FE for the right port).

An automatic power-down feature is controlled independently

on each port by the chip enable (CE) pins.

The CY7C132/CY7C142 are available in 48-pin DIP. The

CY7C136/CY7C146 are available in 52-pin PLCC and PQFP.

CY7C132/CY7C136/CY7C142

2Kx8 Dual-Port Static RAM

•

San Jose

INT

R/W

I/O

BUSY

10R

December 1989 – Revised March 27, 1997

[2]

C132-1

[1]

•

CY7C132/CY7C136

CY7C142/CY7C146

CA 95134

Pin Configuration

BUSY

I/O

R/W

GND

10L

and

Top View

7C132

7C142

DIP

•

fax id: 5201

CY7C146

408-943-2600

R/W

I/O

BUSY

C132-2

10R

are

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