74ABT573CMSA Fairchild Semiconductor, 74ABT573CMSA Datasheet - Page 9

IC LATCH OCT D-TYPE 3ST 20SSOP

74ABT573CMSA

Manufacturer Part Number
74ABT573CMSA
Description
IC LATCH OCT D-TYPE 3ST 20SSOP
Manufacturer
Fairchild Semiconductor
Series
74ABTr
Datasheet

Specifications of 74ABT573CMSA

Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
4.5 V ~ 5.5 V
Independent Circuits
1
Delay Time - Propagation
2.7ns
Current - Output High, Low
32mA, 64mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
©1993 Fairchild Semiconductor Corporation
74ABT573 Rev. 1.5.0
Physical Dimensions
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
10.65
10.00
INDICATOR
(R0.10)
PIN ONE
(R0.10)
7.60
7.40
B
Figure 8. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
2.65 MAX
1.27
0.40
(1.40)
20
1
SEATING PLANE
DETAIL A
0.75
0.25
SCALE: 2:1
0.35
0.51
0.25
13.00
12.60
11.43
X 45°
GAGE PLANE
0.25
M
C
B
A
1.27
0.30
0.10
11
10
NOTES: UNLESS OTHERWISE SPECIFIED
A
A) THIS PACKAGE CONFORMS TO JEDEC
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
D) CONFORMS TO ASME Y14.5M-1994
E) LANDPATTERN STANDARD: SOIC127P1030X265-20L
F) DRAWING FILENAME: MKT-M20BREV3
9
C
0.10 C
MS-013, VARIATION AC, ISSUE E
FLASH OR BURRS.
LAND PATTERN RECOMMENDATION
2.25
1.27
SEE DETAIL A
SEATING PLANE
0.65
www.fairchildsemi.com
0.33
0.20
9.50

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