74ALVCH16373TX Fairchild Semiconductor, 74ALVCH16373TX Datasheet

IC LATCH TRANSP 16BIT 48TSSOP

74ALVCH16373TX

Manufacturer Part Number
74ALVCH16373TX
Description
IC LATCH TRANSP 16BIT 48TSSOP
Manufacturer
Fairchild Semiconductor
Series
74ALVCHr
Datasheet

Specifications of 74ALVCH16373TX

Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
1.65 V ~ 3.6 V
Independent Circuits
2
Delay Time - Propagation
1ns
Current - Output High, Low
24mA, 24mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
© 2002 Fairchild Semiconductor Corporation
74ALVCH16373T
74ALVCH16373
Low Voltage 16-Bit Transparent Latch with Bushold
General Description
The ALVCH16373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear to be transparent to the data when the Latch
Enable (LE) is HIGH. When LE is LOW, the data that meets
the setup time is latched. Data appears on the bus when
the Output Enable (OE) is LOW. When OE is HIGH, the
outputs are in a high impedance state.
The ALVCH16373 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
The 74ALVCH16373 is designed for low voltage (1.65V to
3.6V) V
The 74ALVCH16373 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Order Number
CC
applications with output compatibility up to 3.6V.
Package
Number
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
DS500631
Features
1.65V to 3.6V V
3.6V tolerant control inputs and outputs
Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
t
Uses patented noise/EMI reduction circuitry
Latch-up conforms to JEDEC JED78
ESD performance:
PD
3.6 ns max for 3.0V to 3.6V V
4.5 ns max for 2.3V to 2.7V V
6.8 ns max for 1.65V to 1.95V V
Human body model
Machine model
(I
n
Package Description
to O
n
)
CC
supply operation
200V
2000V
October 2001
Revised February 2002
CC
CC
CC
www.fairchildsemi.com

Related parts for 74ALVCH16373TX

74ALVCH16373TX Summary of contents

Page 1

... MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol © 2002 Fairchild Semiconductor Corporation Features 1.65V to 3.6V V supply operation CC 3.6V tolerant control inputs and outputs ...

Page 2

Connection Diagram www.fairchildsemi.com Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW Latch Enable Input n I –I Bushold Inputs –O Outputs Connect Truth Tables Inputs ...

Page 3

Functional Description The 74ALVCH16373 contains sixteen edge D-type latches with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following ...

Page 4

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V ) (Note 2) 0. Input Diode Current ( Output Diode Current (I ) ...

Page 5

AC Electrical Characteristics Symbol Parameter V CC Min t Pulse Width 3 Setup Time 1 Hold Time 1 Propagation Delay 1.1 PHL PLH Propagation ...

Page 6

AC Loading and Waveforms FIGURE 1. AC Test Circuit (Input Characteristics: f Symbol 3. FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...

Related keywords