74HCT280D,653 NXP Semiconductors, 74HCT280D,653 Datasheet - Page 2

• Manufacturer Part Number: 74HCT280D,653
• Description: IC PARITY GEN/CHKER 9BIT 14SOIC
• Manufacturer: NXP Semiconductors
• Series: 74HCTr

Specifications of 74HCT280D,653

• Number Of Circuits: 9-Bit
• Package / Case: 14-SOIC (0.154", 3.90mm Width)
• Logic Type: Parity Generator/Checker
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Number Of Bits: 9
• Logic Family: HCT
• High Level Output Current: - 6 mA
• Low Level Output Current: 6 mA
• Propagation Delay Time: 45 ns @ 4.5 V
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Input Bias Current (max): 8 uA
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Current - Output High, Low: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 74HCT280D-T; 74HCT280D-T; 933713890653

Philips Semiconductors
FEATURES
GENERAL DESCRIPTION
The 74HC/HCT280 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT280 are 9-bit parity generators or checkers
commonly used to detect errors in high-speed data
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. For HC the condition is V
ORDERING INFORMATION
See
December 1990
SYMBOL PARAMETER
t
C
C
PHL
Word-length easily expanded by cascading
Similar pin configuration to the “180” for easy system
up-grading
Generates either odd or even parity for nine data bits
Output capability: standard
I
9-bit odd/even parity generator/checker
I
PD
CC
f
f
C
V
For HCT the condition is V
i
o
“74HC/HCT/HCU/HCMOS Logic Package Information”
/ t
CC
PD
= input frequency in MHz
L
category: MSI
= output frequency in MHz
PLH
(C
= output load capacitance in pF
P
= supply voltage in V
is used to determine the dynamic power dissipation (P
D
L
= C
V
propagation delay
input capacitance
power dissipationcapacitance per package
amb
CC
PD
I
I
n
n
2
to
to
= 25 C; t
V
f
o
CC
E
O
) = sum of outputs
2
f
r
i
= t
I
= GND to V
I
f
= GND to V
= 6 ns
(C
L
V
CC
2
CC
CC
f
o
) where:
1.5 V
CONDITIONS
C
notes 1 and 2
2
.
L
transmission or data retrieval systems. Both even and odd
parity outputs are available for generating or checking
even or odd parity up to 9 bits.
The even parity output (
of data inputs (I
is HIGH when an odd number of data inputs are HIGH.
Expansion to larger word sizes is accomplished by tying
the even outputs (
data inputs of the final stage. For a single-chip 16-bit
even/odd parity generator/checker, see
PC74HC/HCT7080.
APPLICATIONS
= 15 pF; V
D
25-line parity generator/checker
81-line parity generator/checker
in W):
CC
= 5 V
0
to I
8
E
) are HIGH. The odd parity output (
) of up to nine parallel devices to the
17
20
3.5
65
E
) is HIGH when an even number
HC
TYPICAL
74HC/HCT280
Product specification
18
22
3.5
65
HCT
ns
ns
pF
pF
UNIT
0
)