ISPLSI5256VE-100LT128I Lattice Semiconductor Corp., ISPLSI5256VE-100LT128I Datasheet

ISPLSI5256VE-100LT128I

Manufacturer Part Number

ISPLSI5256VE-100LT128I

Description

Manufacturer

Lattice Semiconductor Corp.

Datasheets

1.ISPLSI5256VE-100LT128I.pdf (24 pages)

2.ISPLSI5256VE-100LT128I.pdf (24 pages)

Specifications of ISPLSI5256VE-100LT128I

Case

QFP100

Date_code

03+

Current page: 1 of 24
Download datasheet (248Kb)

• Second Generation SuperWIDE HIGH DENSITY

• HIGH PERFORMANCE E

• IN-SYSTEM PROGRAMMABLE

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND

• ARCHITECTURE FEATURES

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

5256ve_10

Features

IN-SYSTEM PROGRAMMABLE LOGIC DEVICE

— 3.3V Power Supply

— User Selectable 3.3V/2.5V I/O

— 12000 PLD Gates / 256 Macrocells

— Up to 144 I/O Pins

— 256 Registers

— High-Speed Global Interconnect

— SuperWIDE Generic Logic Block (32 Macrocells) for

— SuperWIDE Input Gating (68 Inputs) for Fast

— PCB Efficient Ball Grid Array (BGA) Package Options

— Interfaces with Standard 5V TTL Devices

—

— TTL/3.3V/2.5V Compatible Input Thresholds and

— Electrically Erasable and Reprogrammable

— Non-Volatile

— Programmable Speed/Power Logic Path Optimization

— Increased Manufacturing Yields, Reduced Time-to-

— Reprogram Soldered Devices for Faster Debugging

3.3V IN-SYSTEM PROGRAMMABLE

— Enhanced Pin-Locking Architecture with Single-

— Wrap Around Product Term Sharing Array Supports

— Macrocells Support Concurrent Combinatorial and

— Macrocell Registers Feature Multiple Control

— Four Dedicated Clock Input Pins Plus Macrocell

— Programmable I/O Supports Programmable Bus

— Four Global Product Term Output Enables, Two

Market, and Improved Product Quality

Optimum Performance

Counters, State Machines, Address Decoders, etc.

Output Levels

Level Global Routing Pool and SuperWIDE GLBs

up to 35 Product Terms Per Macrocell

Registered Functions

Options Including Set, Reset and Clock Enable

Product Term Clocks

Hold, Pull-up, Open Drain and Slew Rate Options

Global OE Pins and One Product Term OE per

Macrocell

max = 165 MHz Maximum Operating Frequency

pd = 6.0 ns Propagation Delay

CMOS

TECHNOLOGY

The ispLSI 5000VE Family of In-System Programmable

High Density Logic Devices is based on Generic Logic

Blocks (GLBs) of 32 registered macrocells and a single

Global Routing Pool (GRP) structure interconnecting the

GLBs.

Outputs from the GLBs drive the Global Routing Pool

(GRP) between the GLBs. Switching resources are pro-

vided to allow signals in the Global Routing Pool to drive

any or all the GLBs in the device. This mechanism allows

fast, efficient connections across the entire device.

Each GLB contains 32 macrocells and a fully populated,

programmable AND-array with 160 logic product terms

and three extra control product terms. The GLB has 68

inputs from the Global Routing Pool which are available

in both true and complement form for every product term.

The 160 product terms are grouped in 32 sets of five and

sent into a Product Term Sharing Array (PTSA) which

allows sharing up to a maximum of 35 product terms for

a single function. Alternatively, the PTSA can be by-

passed for functions of five product terms or less. The

three extra product terms are used for shared controls:

reset, clock, clock enable and output enable.

Functional Block Diagram

ispLSI 5000VE Description

3.3V SuperWIDE™ High Density PLD

Logic Block

Generic

Input Bus

ispLSI

Global Routing Pool

In-System Programmable

(GRP)

Logic Block

Generic

Input Bus

5256VE

January 2002

Boundary

Interface

Scan

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