74ABT899CMSAX Fairchild Semiconductor, 74ABT899CMSAX Datasheet - Page 2

• Manufacturer Part Number: 74ABT899CMSAX
• Description: TXRX W/GENERATOR&CHECKER 28SSOP
• Manufacturer: Fairchild Semiconductor
• Series: 74ABTr

Specifications of 74ABT899CMSAX

• Logic Type: Parity Generator/Checker
• Number Of Circuits: 9-Bit
• Current - Output High, Low: 32mA, 64mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Pin Descriptions
Function Table
H
L
X
Note 1: O/E
A
B
APAR, BPAR
ODD/EVEN
GBA, GAB
SEL
LEA, LEB
ERRA, ERRB
LOW Voltage Level
HIGH Voltage Level
Immaterial
0
0
Pin Names
–A
–B
GAB GBA SEL LEA LEB
H
H
H
H
H
H
7
7
L
L
L
L
L
ODD/EVEN
H
H
H
H
H
H
L
L
L
L
L
Inputs
A Bus Data Inputs/Data Outputs
B Bus Data Inputs/Data Outputs
A and B Bus Parity Inputs/Outputs
ODD/EVEN Parity Select,
Active LOW for EVEN Parity
Output Enables for A or B Bus,
Active LOW
Select Pin for Feed-Through or
Generate Mode, LOW for Generate
Mode
Latch Enables for A and B Latches,
HIGH for Transparent Mode
Error Signals for Checking Generated
Parity with Parity In, LOW if Error
Occurs
X
H
H
H
H
L
L
L
L
L
L
X
H
X
X
H
H
H
H
H
L
L
Descriptions
X
H
H
H
H
H
X
H
L
L
L
Busses A and B are 3-STATE.
Generates parity from B[0:7] based on O/E (Note 1). Generated parity
Generated parity checked against BPAR and output as ERRB.
Generates parity from B[0:7] based on O/E. Generated parity
ated parity checked against BPAR and output as ERRB. Generated parity also
fed back through the A latch for generate/check as ERRA.
Generates parity from B latch data based on O/E. Generated parity
Generated parity checked against latched BPAR and output as ERRB.
BPAR/B[0:7]
against BPAR and output as ERRB.
BPAR/B[0:7]
Feed-through mode. Generated parity checked against BPAR and output as
ERRB. Generated parity also fed back through the A latch for generate/check as
ERRA.
Generates parity for A[0:7] based on O/E. Generated parity
ated parity checked against APAR and output as ERRA.
Generates parity from A[0:7] based on O/E. Generated parity
ated parity checked against APAR and output as ERRA. Generated parity also
fed back through the B latch for generate/check as ERRB.
Generates parity from A latch data based on O/E. Generated parity
Generated parity checked against latched APAR and output as ERRA.
APAR/A[0:7]
Feed-through mode. Generated parity checked against APAR and output as
ERRA.
APAR/A[0:7]
Feed-through mode. Generated parity checked against APAR and output as
ERRA. Generated parity also fed back through the B latch for generate/check as
ERRB.
APAR/A0:7] Feed-through mode. Generated parity checked
APAR/A[0:7]
BPAR/B[0:7]
BPAR/B[0:7]
2
Functional Description
The ABT899 has three principal modes of operation which
are outlined below. These modes apply to both the A-to-B
and B-to-A directions.
• Bus A (B) communicates to Bus B (A), parity is gener-
• Bus A (B) communicates to Bus B (A) in a feed-through
• Independent Latch Enables (LEA and LEB) allow other
ated and passed on to the B (A) Bus as BPAR (APAR). If
LEB (LEA) is HIGH and the Mode Select (SEL) is LOW,
the parity generated from B[0:7] (A[0:7]) can be checked
and monitored by ERRB (ERRA).
mode if SEL is HIGH. Parity is still generated and
checked as ERRA and ERRB in the feed-through mode
(can be used as an interrupt to signal a data/parity bit
error to the CPU).
permutations of generating/checking (see Function
Table below).
Operation
BPAR. Gener-
APAR. Gener-
BPAR. Gener-
APAR.
BPAR.
APAR.