PI74AVC16835AEX Pericom Semiconductor, PI74AVC16835AEX Datasheet
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PI74AVC16835AEX
Manufacturer Part Number
PI74AVC16835AEX
Description
Manufacturer
Pericom Semiconductor
Datasheet
1.PI74AVC16835AEX.pdf
(10 pages)
Specifications of PI74AVC16835AEX
Pack_quantity
1500
Comm_code
85423990
Lead_time
994
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
Product Pin Configuration
Product Features
• Very high-speed, low-noise universal bus driver with
• Meets PC133 SDRAM Registered DIMM specification
• Implements output impedance control for low-noise and
• Fast Propagation Delay:
• V
• Packaging (Pb-free and Green available):
embedded resistor outputs
heavy-load applications
2.5ns max. for 50pF test load
– 56-pin, 240 mil wide plastic TSSOP (A)
CC
= 3.3V or 2.5V or 1.8V
08-0291
GND
GND
GND
GND
VDD
VDD
Y10
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y11
OE
NC
NC
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
LE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
NC
A1
GND
A2
A3
VDD
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VDD
A16
A17
GND
A18
CLK
LE
1
Product Description
Data flow from A to Y is controlled by Output Enable (OE). The device
operates in the transparent mode when LE is HIGH. The A data is
latched if CLK is held at a high or low logic level. If LE is LOW, the
A-bus is stored in the latch/flip-flop on the low-to-high transition of
CLK. When OE is HIGH, the outputs are in the high-impedance state.
The PI74AVC16835 bus driver is designed to drive an array of 133
MHz synchronous memory chips, with minimal undershoot/
overshoot noise, and to meet the input signal rise/fall time requirement
of memory chips.
The output drivers of this part have an embedded series-resistor. For
DIMM module design, no external series termination resistors near
the buffer drivers or any other termination resistors are required. This
feature simplifies DIMM module layout design, and results in cost
savings.
18-Bit Universal Bus Driver
with 3-State Outputs
PI74AVC16835
PS8373H
11/05/08