PI90LV022LEX Pericom Semiconductor, PI90LV022LEX Datasheet

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PI90LV022LEX

Manufacturer Part Number
PI90LV022LEX
Description
Manufacturer
Pericom Semiconductor
Datasheet

Specifications of PI90LV022LEX

Pack_quantity
3000
Comm_code
85423990
Lead_time
994
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
Features
• Meets or Exceeds the Requirements of ANSI TIA/
• Designed for Signaling Rates up to 650 Mbit/s (325 MHz)
• Operates from a 3.3V Supply: –40°C to +85°C
• Low Voltage Differential Signaling with Output Voltages
• Accepts ±350mV differential inputs
• Wide common mode input voltage range: 0.2V to 2.7V
• Output drivers are high impedance when disabled or
• Inputs are open, short, and terminated fail safe
• Propagation Delay Time: 3.5ns
• ESD protection is 10kV on bus pins
• Bus Pins are High Impedance when disabled or
• TTL Inputs are 5V I/O Tolerant
• Power Dissipation at 400Mbit/s less than 150mW
• Industrial temperature rating
• Packaging (Pb-free & Green available):
Block Diagram
EIA-644-1995
of ±350mV into:
- 100 Ohm load (PI90LV022)
- 50 Ohm load Bus LVDS Signaling (PI90LVB022)
when V
with V
- 16-pin TSSOP (L)
08-0295
CC
1A
1B
2A
2B
CC
less than 1.5V
≤ 1.5V
+
+
S0 S1
1DE
1Y
1Z
2Y
2Z
2DE
1
Description
The PI90LV022 and PI90LVB022 are differential line drivers and
receivers that use Low Voltage Differential Signaling (LVDS) to
achieve signaling rates as high as 650 Mbps. The receiver outputs
can be switched to either or both drivers through the multiplexer
control signals S0 and S1. This allows the flexibility to perform
splitter or signal routing functions with a single device.
The LVDS standard provides a minimum differential output voltage
magnitude of 247mV into a 100 Ohm load and receipt of 100mV DC
signals with up to 1V of ground potential difference between a
transmitter and receiver. The PI90LVB022 doubles the output drive
current to achieve Bus LVDS signaling levels with a 50 Ohm load.
A doubly terminated Bus LVDS line enables multi-point configura-
tions. Switching between channels does not create false transitions
on the outputs.
The intended application of these devices and signaling technique
is for both point-to-point base-band (PI90LV022) and multipoint
(PI90LVB022) data transmissions over controlled impedance media.
Pin Configuration
GND
1DE
1B
S0
S1
2B
1A
2A
PI90LV022, PI90LVB022
1
2
3
4
5
6
7
8
16-Pin
L
LVDS Mux/Repeater
16
15
14
13
12
10
11
9
V CC
V CC
1Y
1Z
2DE
2Z
2Y
GND
PS8488C
10/28/09

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