PI90LVT14L Pericom Semiconductor, PI90LVT14L Datasheet

PI90LVT14L

Manufacturer Part Number

PI90LVT14L

Description

20/1:5 LVDS CLOCK DISTRIBUTION; EOL: REPL: PI90LVT14LE; LTB(d/m/y):30/11/20

Manufacturer

Pericom Semiconductor

Datasheets

1.PI90LVT14Q.pdf (6 pages)

2.PI90LVT14L.pdf (6 pages)

3.PI90LVT14L.pdf (7 pages)

Specifications of PI90LVT14L

Pack_quantity

Comm_code

85423990

Lead_time

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Function Table

1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2

Pin Descriptions

Features

• Meets and Exceeds the Requirements of ANSI

• Designed for clocking rates up to 320MHz

• Operates from a single 3.3V Supply

• Low Voltage Differential Signaling (LVDS) with Output

• Choice between LVDS or TTL clock input

• Synchronous Enable/Disable

• Clock outputs default LOW when inputs open

• Multiplexed clock input

• 50ps Output-to-Output Skew

• 475ps typical propagation delay

• Bus Pins are high impedance when disabled or with

• TTL inputs are 5V Tolerant

• Power Dissipation at 400Mbits/s of 150mW

• Function compatible to Motorola (PECL)

• >9kV ESD Protection

• 20-pin TSSOP (L) and QSOP (Q) packages

* On next negative transition of CLK, or SCLK

TIA/EIA-644-1995

Voltages of ±350mV into a 100Ω load

- Internal 300kΩ pullup resistor on input pins

- CLK and CLK have 110Ω internal termination (PI90LVT14)

MC100EL14 and Micrel/Synergy (PECL)

SY100EL14V

↓

less than 1.5V

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Description

The PI90LV14 implements low voltage differential signaling (LVDS)

to achieve clocking rates as high as 320MHz with low skew.

The PI90LV14 is a low-skew 1:5 clock distribution chip which

incorporates multiplexed clock inputs to allow for distribution of a

lower-speed, single-ended clock or a high-speed system clock.

When LOWthe SEL pin will select the differential clock input.

The common enable (EN) is synchronous so that the outputs will

only be enabled/disabled when they are already in the LOW state.

This avoids any chance of generating a runt clock pulse when the

device is enabled/disabled as can happen with an asynchronous

control. Because the internal flip-flop is clocked on the falling edge

of the input clock, all associated specification limits are referenced

to the negative edge of the clock input.

The intended application of these devices and signaling technique

is for high-speed clock distribution between boards.

PI90LV14 Block Diagram

CLK1

CLK2

CLK3

CLK4

CLK5

OUT+

OUT–

OUT+

OUT–

OUT+

OUT–

OUT+

OUT–

OUT+

OUT–

PI90LV14/PI90LVT14

1:5 Clock Distribution

PS8538

Ω

GND

SCLK

CLK

GND

SEL

GND

04/25/01

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