CY7C1302DV25-167BZXC Cypress Semiconductor Corporation., CY7C1302DV25-167BZXC Datasheet

CY7C1302DV25-167BZXC

Manufacturer Part Number

CY7C1302DV25-167BZXC

Description

BGA 165/512KX18 2.5V QDR SRAM (2-WORD BURST)

Manufacturer

Cypress Semiconductor Corporation.

Datasheets

1.CY7C1302DV25-167BZXC.pdf (18 pages)

2.CY7C1302DV25-167BZXC.pdf (18 pages)

3.CY7C1302DV25-167BZXC.pdf (18 pages)

Specifications of CY7C1302DV25-167BZXC

Pack_quantity

136

Comm_code

85423245

Lead_time

Eccn

3A991B2A

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Meier Automation Equipment Co., Limited

Part Number:

CY7C1302DV25-167BZXC

Manufacturer:

CYPRESS/赛普拉斯

Quantity:

20 000

Current page: 1 of 18
Download datasheet (415Kb)

Cypress Semiconductor Corporation

Document #: 38-05625 Rev. *A

Features

Configurations

CY7C1302DV25 – 512K x 18

• Separate independent Read and Write data ports

• 167-MHz clock for high bandwidth

• 2-word burst on all accesses

• Double Data Rate (DDR) interfaces on both Read and

• Two input clocks (K and K) for precise DDR timing

• Two input clocks for output data (C and C) to minimize

• Single multiplexed address input bus latches address

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• 2.5V core power supply with HSTL Inputs and Outputs

• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)

• Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–1.9V)

• JTAG Interface

— Supports concurrent transactions

— 2.5 ns Clock-to-Valid access time

Write ports (data transferred at 333 MHz) @ 167 MHz

— SRAM uses rising edges only

clock-skew and flight-time mismatches.

inputs for both Read and Write ports

Logic Block Diagram (

(17:0)

BWS

WPS

BWS

Vref

[17:0]

Address

Control

Logic

CY7C1302DV25

CLK

Gen.

•

198 Champion Court

)

9-Mbit Burst of Two Pipelined SRAMs

Write

Data Reg

256Kx18

Memory

Array

Read Data Reg.

Functional Description

The CY7C1302DV25 is a 2.5V Synchronous Pipelined SRAM

equipped with QDR™ architecture. QDR architecture consists

of two separate ports to access the memory array. The Read

port has dedicated data outputs to support Read operations

and the Write Port has dedicated data inputs to support Write

operations. Access to each port is accomplished through a

common address bus. The Read address is latched on the

rising edge of the K clock and the Write address is latched on

the rising edge of K clock. QDR has separate data inputs and

data outputs to completely eliminate the need to “turn-around”

the data bus required with common I/O devices. Accesses to

the CY7C1302DV25 Read and Write ports are completely

independent of one another. All accesses are initiated

synchronously on the rising edge of the positive input clock

(K). In order to maximize data throughput, both Read and

Write ports are equipped with DDR interfaces. Therefore, data

can be transferred into the device on every rising edge of both

input clocks (K and K) and out of the device on every rising

edge of the output clock (C and C, or K and K in a single clock

domain) thereby maximizing performance while simplifying

system design. Each address location is associated with two

18-bit words that burst sequentially into or out of the device.

Depth expansion is accomplished with a Port Select input for

each port. Each Port Select allows each port to operate

independently.

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

256Kx18

Memory

Array

Write

Data Reg

•

San Jose

with QDR™ Architecture

Reg.

Address

Control

Logic

CA 95134-1709

Reg.

Revised March 23, 2006

CY7C1302DV25

RPS

•

(17:0)

[17:0]

408-943-2600

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