LS7212 LSI Computer Systems, LS7212 Datasheet

LS7212

Manufacturer Part Number

LS7212

Description

PROGRAMMABLE DIGITAL DELAY TIMER

Manufacturer

LSI Computer Systems

Datasheet

1.LS7212.pdf (8 pages)

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7211-041700-1

DESCRIPTION:

The LS7211/LS7212 are monolithic CMOS integrated cir-

cuits for generating digitally programmable delays. The de-

lay is controlled by 8 binary weighted inputs, WB0-WB7, in

conjunction with an applied clock or oscillator frequency.

The programmed time delay manifests itself in the Delay

Output (OUT) as a function of the Operating Mode selected

by the Mode Select inputs A and B: One-Shot, Delayed

Operate, Delayed Release or Dual Delay. The time delay is

initiated by a transition of the Trigger Input (TRIG).

I/O DESCRIPTION:

MODE SELECT Inputs (A &B, Pins 1 & 2)

The 4 operating modes are selected by Inputs A and B

according to Table 1

Each input has an internal pull-up resistor of about 500K .

One-Shot Mode (OS)

A positive transition at the TRIG input causes OUT to

switch low without delay and starts the delay timer. At the

end of the programmed delay timeout, OUT switches high.

If a delay timeout is in progress when a positive transition

occurs at the TRIG input, the delay timer will be restarted.

A negative transition at the TRIG input has no effect.

Delayed Operate Mode (DO)

A positive transition at the TRIG input starts the delay tim-

er. At the end of the delay timeout, OUT switches low. A

negative transition at the TRIG input causes OUT to switch

high without delay. OUT is high when TRIG is low.

FEATURES:

• 8-bit programmable delay from nanoseconds to days

• On chip oscillator (RC or Crystal) or external clock time base

• Selectable prescaler for real time delay generation based

• Four operating modes

• Reset input for delay abort

• Low quiescent and operating current

• Direct relay drive

• +4V to +18V operation (V

• LS7211/LS7212 (DIP), LS7211-S/LS7212-S (SOIC)-See Figure 1

A3800

LSI/CSI

U L

on 50Hz/60Hz time base or 32.768KHz watch crystal

LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747

TABLE 1. MODE SELECTION

PROGRAMMABLE DIGITAL DELAY TIMER

MODE

One-Shot (OS)

Delayed Operate (DO)

Delayed Release (DR)

Dual Delay (DD)

-V

)

Delayed Release Mode (DR)

A negative transition at the TRIG input starts the delay tim-

er. At the end of the delay timeout, OUT switches high. A

postive transition at the TRIG input causes OUT to switch

low without delay. OUT is low when TRIG is high.

Dual Delay Mode (DD)

A positive or negative transition at the TRIG input starts

the delay timer. At the end of the delay timeout, OUT

switches to the logic state which is the inverse of the TRIG

input. If a delay timeout is in progress when a transition

occurs at the TRIG input, the delay timer is restarted.

XTLI/CLOCK

RC/CLOCK

RCS/CLKS

LS7211-7212

R E S E T

P S C L S

XTLO

OUT

(+V)

(-V)

(+V)

(631) 271-0400 FAX (631) 271-0405

PIN ASSIGNMENT - TOP VIEW

FIGURE 1

June 1997

TRIG

WB0

WB1

WB2

WB3

WB4

WB5

WB6

WB7

WB0

WB1

WB2

WB3

WB4

WB5

WB6

WB7

Related parts for LS7212

LS7212 Summary of contents

Page 1

... DD • LS7211/LS7212 (DIP), LS7211-S/LS7212-S (SOIC)-See Figure 1 DESCRIPTION: The LS7211/LS7212 are monolithic CMOS integrated cir- cuits for generating digitally programmable delays. The de- lay is controlled by 8 binary weighted inputs, WB0-WB7, in conjunction with an applied clock or oscillator frequency. The programmed time delay manifests itself in the Delay ...

Page 2

... RCS/CLKS input (Pin 5); the internal oscillator mode is selected by applying a high level to the RCS/CLKS input. LS7212 TIME BASE Input (XTLI/CLOCK, Pin 4) For LS7212, the basic timing clock is applied to the XLTI/ CLOCK input from either an external clock source or gener- ated by an internal crystal oscillator by connecting a crystal between XTLI/CLOCK input and the XTLO output (Pin 5) ...

Page 3

ABSOLUTE MAXIMUM RATINGS: (All voltages referenced Supply Voltage Voltage (Any Pin) Operating Temperature Storage Temperature ELECTRICAL CHARACTERISTICS (Voltages referenced to Vss) Characteristic SYMBOL Supply Voltage V DD Supply Current I DD Input Voltages: Trigger Low V Trigger ...

Page 4

... TRIG Set-Up Time Set-Up Time t 2 WB0 - WB7 Set-Up Time t 3 Clock to Out Delay 500K 500K B 2 TRIG 18 500K RESET 7 CLOCK/RC/XTLI 4 OSC XTLO(LS7212 RCS/CLKS(LS7211) 500K PSCLS 6 FIGURE 2. LS7211/LS7212 BLOCK DIAGRAM V DD Min Max Min 4.0 - 1.3 - 10.0 - 4.0 - 18.0 - 6.0 - 4.0 - 2.3 - 10.0 - 7.0 - 18.0 - 11.0 - 4.0 - 1 ...

Page 5

Clock t 1 TRIG Delayed Operate A WB0-WB7 OUT Note 1. TRIG input is clocked in by the negative edge of external clock. Note 2. Inputs A, B ...

Page 6

10K ƒ µ ƒ ...

Page 7

... S1 high: Delay increment = 1m; Maximum Delay = 255m FIGURE 9. PROGRAMMABLE ACCURATE REAL-TIME DELAY GENERATION WB0 16 WB1 TRIG 15 XTLI WB2 14 WB3 13 WB4 XTLO 12 WB5 11 WB6 PSCLS 10 WB7 LS7212 RESET Vss OUT +V 3 1s/1m 2s/2m 4s/4m 8s/ seconds m = minutes ...

Page 8

CASE 1. MODE = DO or DR; PRESCALE FACTOR this setup a frequency division of the input clock, ƒ factor 257, in increments of 1 can be obtained ...

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