M37212 Mitsubishi, M37212 Datasheet - Page 19

• Manufacturer Part Number: M37212
• Description: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
• Manufacturer: Mitsubishi

8.3 INTERRUPTS
Interrupts can be caused by 14 different sources consisting of 4 ex-
ternal, 8 internal, 1 software, and reset. Interrupts are vectored inter-
rupts with priorities as shown in Table 8.3.1. Reset is also included in
the table because its operation is similar to an interrupt.
When an interrupt is accepted,
Other interrupts are disabled when the interrupt disable flag is set to
“1.”
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit. The interrupt request bits are
in interrupt request registers 1 and 2 and the interrupt enable bits are
in interrupt control registers 1 and 2. Figures 8.3.2 to 8.3.6 show the
interrupt-related registers.
Interrupts other than the BRK instruction interrupt and reset are ac-
cepted when the interrupt enable bit is “1,” interrupt request bit is “1,”
and the interrupt disable flag is “0.” The interrupt request bit can be
set to “0” by a program, but not set to “1.” The interrupt enable bit can
be set to “0” and “1” by a program.
Reset is treated as a non-maskable interrupt with the highest priority.
Figure 8.3.1 shows interrupt control.
Rev. 1.0
Table 8.3.1 Interrupt Vector Addresses and Priority
Priority
The contents of the program counter and processor status regis-
ter are automatically stored into the stack.
The interrupt disable flag I is set to “1” and the corresponding
interrupt request bit is set to “0.”
The jump destination address stored in the vector address enters
the program counter.
10
11
12
13
14
1
2
3
4
5
6
7
8
9
Reset
OSD interrupt
INT2 external interrupt
INT1 external interrupt
Timer 4 interrupt
f(X
V
Timer 3 interrupt
Timer 2 interrupt
Timer 1 interrupt
Serial I/O interrupt
Multi-master I
INT3 external interrupt
BRK instruction interrupt
SYNC
IN
)/4096 interrupt
interrupt
2
Interrupt Source
C-BUS interface interrupt
M37212M4/M8–XXXSP, M37212M6–XXXSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
Vector Addresses
FFED
FFDF
FFFD
FFEF
FFEB
FFFF
FFFB
FFE9
FFE7
FFE5
FFF9
FFF5
FFF3
FFF1
16
16
16
16
16
16
16
16
16
16
16
16
16
16
, FFFE
, FFFC
, FFF8
, FFF4
, FFF2
, FFF0
, FFEE
, FFEC
, FFEA
, FFE8
, FFE6
, FFE4
, FFDE
, FFFA
8.3.1 Interrupt Causes
(1) V
(2) INT1 to INT3 external interrupts
(3) Timers 1 to 4 interrupts
The V
the vertical sync signal.
The OSD interrupt occurs after character block display to the
CRT is completed.
The INT1 to INT3 interrupts are external interrupt inputs, the sys-
tem detects that the level of a pin changes from LOW to HIGH or
from HIGH to LOW, and generates an interrupt request. The in-
put active edge can be selected by bits 3 to 5 of the interrupt
input polarity register (address 00F9
change from LOW to HIGH is detected; when it is “1,” a change
from HIGH to LOW is detected. Note that both bits are cleared to
“0” at reset.
An interrupt is generated by an overflow of timers 1 to 4.
16
16
16
16
16
16
16
16
16
16
16
16
16
16
SYNC
SYNC
Non-maskable
Active edge selectable
Active edge selectable
Active edge selectable
Non-maskable
, OSD interrupts
interrupt is an interrupt request synchronized with
with ON-SCREEN DISPLAY CONTROLLER
MITSUBISHI MICROCOMPUTERS
M37212EFSP/FP
Remarks
16
) : when this bit is “0,” a
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