HDSP-390X Agilent(Hewlett-Packard), HDSP-390X Datasheet - Page 41

• Manufacturer Part Number: HDSP-390X
• Description: 20 mm (0.8 inch) Seven Segment Displays
• Manufacturer: Agilent(Hewlett-Packard)

Likewise, the Vtt plane must also
be bypassed equally well.
configuration, the logic outputs
are in the PECL (positive ECL)
states. Commercial translation
chips are available which will
translate PECL between TTL and
CMOS.
The GLlink has several option
pins which set the modes of
operation. Common to both the
Tx and the Rx are M20SEL, DIV0,
and DIV1, FLAGSEL, and
LOOPEN. Local to the Tx are
MDFSEL, EHCLKSEL, and
HCLKON. While local to the Rx
are EQEN and TCLKSEL. These
pins are all I-ECL, and can be set
as described below.
M20SEL = 0/1 sets the width of
the frame to 16/20 bits.
DIV1 / DIV0 = set the frequency
bands of operation. Refer to the
Setting the Operating Data Rate
Range section for frequency band
selection. It is recommended that
applications near the ends of the
bands have jumpers for DIV0 and
DIV1 inputs, so that the board
can accommodate possible lot-to-
lot band variations over the life of
the board design.
FLAGSEL = 0/1 selects either the
flag bit is reserved for error
detection by the link, or as an
extra bit available for the user.
In the positive 5 V supply
Mode Options
Figure 23: Methods of Interfacing O-BLL and I-H50.
OBLL
OBLL
OBLL
OBLL
C) DIFFERENTIAL DRIVE O-BLL TO ECL
D) SINGLE-ENDED DRIVE O-BLL TO ECL
150
150
150
150
A) SINGLE-ENDED DRIVE O-BLL TO I-H50 INTERFACE
150
B) DIFFERENTIAL DRIVE O-BLL TO I-H50
150
150
150
Z
Z
Z
Z
Z
Z
O
O
O
O
O
O
50
= 50
= 50
= 50
50
= 50
= 50
= 50
82
V
50
TT
-1.3 V
-1.3 V
(-2 V)
50
130
50
IH50
IH50
ECL
ECL
613