A1010B ACTEL [Actel Corporation], A1010B Datasheet - Page 15

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A1010B

Manufacturer Part Number
A1010B
Description
ACT 1 Series FPGAs
Manufacturer
ACTEL [Actel Corporation]
Datasheet

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A CT 1 Timi ng C ha ra ct er i s t i cs
(Worst-Case Commercial Conditions, V
Logic Module Propagation Delays
Parameter
t
t
t
t
t
Predicted Routing Delays
t
t
t
t
t
Sequential Timing Characteristics
t
t
t
t
t
t
t
f
Notes:
1.
2.
3.
4.
PD1
PD2
CO
GO
RS
RD1
RD2
RD3
RD4
RD8
SUD
HD
SUENA
HENA
WCLKA
WASYN
A
MAX
4
V
Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based
on actual routing delay measurements performed on the device prior to shipment.
Setup times assume fanout of 3. Further testing information can be obtained from the DirectTime Analyzer utility.
The Hold Time for the DFME1A macro may be greater than 0 ns. Use the Designer 3.0 or later Timer to check the Hold Time for this macro.
CC
= 3.0 V for 3.3V specifications.
Description
Single Module
Dual Module Macros
Sequential Clk to Q
Latch G to Q
Flip-Flop (Latch) Reset to Q
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Flip-Flop (Latch) Data Input Setup
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Setup
Flip-Flop (Latch) Enable Hold
Flip-Flop (Latch) Clock Active Pulse
Width
Flip-Flop (Latch)
Asynchronous Pulse Width
Flip-Flop Clock Input Period
Flip-Flop (Latch) Clock
Frequency (FO = 128)
2
3
CC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
‘–3’ Speed
14.2
5.5
0.0
5.5
0.0
6.8
6.8
= 4.75 V, T
2.9
6.8
2.9
2.9
2.9
0.9
1.4
2.1
3.1
6.6
70
‘–2’ Speed
16.7
6.4
0.0
6.4
0.0
8.0
8.0
J
= 70 C)
3.4
7.8
3.4
3.4
1.1
1.7
2.5
3.6
7.7
3.4
60
18.9
‘–1’ Speed ‘Std’ Speed 3.3 V Speed
7.2
0.0
7.2
0.0
9.0
9.0
1
3.8
8.8
3.8
3.8
3.8
1.2
1.9
2.8
4.1
8.7
53
10.5
10.5
22.3
8.5
0.0
8.5
0.0
A C T
10.4
10.2
4.5
4.5
4.5
4.5
1.4
2.2
3.3
4.8
45
1 S eri es FPG As
10.0
10.0
20.0
0.0
0.0
9.8
9.8
15.1
14.8
6.5
6.5
6.5
6.5
2.0
3.2
4.8
7.0
50
1-297
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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