AS5245 AMSCO [austriamicrosystems AG], AS5245 Datasheet - Page 13

• Manufacturer Part Number: AS5245
• Manufacturer: AMSCO [austriamicrosystems AG]

AS5245
Data Sheet - D e t a i l e d D e s c r i p t i o n
8.2 Synchronous Serial Interface (SSI)
Figure 5. Synchronous Serial Interface with Absolute Angular Position Data
If CSn changes to logic low, Data Out (DO) will change from high impedance (tri-state) to logic high and the read-out will be initiated.
8.2.1 Serial Data Contents
D11:D0 – Absolute angular position data (MSB is clocked out first).
OCF – (Offset Compensation Finished). Logic high indicates the finished Offset Compensation Algorithm.
COF – (Cordic Overflow). Logic high indicates an out of range error in the CORDIC part. When this bit is set, the data at D9:D0 is invalid. The
absolute output maintains the last valid angular value. This alarm may be resolved by bringing the magnet within the X-Y-Z tolerance limits.
LIN – (Linearity Alarm). Logic high indicates that the input field generates a critical output linearity. When this bit is set, the data at D9:D0 may still
be used, but can contain invalid data. This warning may be resolved by bringing the magnet within the X-Y-Z tolerance limits.
Even Parity – Bit for transmission error detection of bits 1…17 (D11…D0, OCF, COF, LIN, MagINC, MagDEC). Placing the magnet above the
chip, angular values increase in clockwise direction by default.
Data D11:D0 is valid, when the status bits have the following configurations:
Table 8. Status Bit Outputs
Note: MagInc=MagDec=1 is only recommended in YELLOW mode
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CSn
CLK
After a minimum time t
Each subsequent rising CLK edge shifts out one bit of data.
The serial word contains 18 bits, the first 12 bits are the angular information D[11:0], the subsequent 6 bits contain system information,
about the validity of data such as OCF, COF, LIN, Parity and Magnetic Field status (increase/decrease).
A subsequent measurement is initiated by a “high” pulse at CSn with a minimum duration of t
DO
OCF
1
t
DO active
t
CLKFE
1
D11
CLK FE
T
CLK/2
D10
COF
, data is latched into the output shift register with the first falling edge of CLK.
t
0
DO valid
D9
D8
D7
Angular Position Data
D6
D5
LIN
0
8
D4
D3
Revision 1.3
(see Table 9)
D2
D1
Mag INC
0
0
1
1
D0 OCF COF LIN
Status Bits
CSn
.
Mag
INC
Mag DEC
0
1
0
1
DEC
Mag
18
Even
PAR
t
DO Tristate
t
CSn
Even checksum of bits
t
CLKFE
Parity
1:15
1
D11
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