CXA3286 Sony Corporation, CXA3286 Datasheet - Page 12

• Manufacturer Part Number: CXA3286
• Description: 8-bit 160MSPS Flash A/D Converter
• Manufacturer: Sony Corporation

Description of Operation Modes
The CXA3286R has two types of operation modes which are selected with Pin 45 (SELECT1).
1. DMUX mode (See Application Circuit 1-(1), (2) and (3).)
Set the SELECT1 pin to Vcc for this mode. In this mode, the clock frequency is divided by 2 in the IC, and the
data is output after being demultiplexed by this 1/2 frequency-divided clock. The 1/2 frequency-divided clock,
which has adequate setup time and hold time for the output data, is output from the clock output pin.
When using the multiple CXA3286R in DMUX mode, the start timing of the 1/2 frequency-divided clocks
becomes out of phase, producing operation such as that shown in the example on the next page. As a
countermeasure, the CXA3286R has a function that resets the 1/2 frequency-divided clocks.
When resetting this 1/2 frequency-divided clock, the low level of the reset signal should be input to the
RESETN pin (Pin 46 or 48). The reset signal requires the setup time (T_rs ≥ 1.0ns) and hold time (T_rh ≥
–0.5ns) to the clock rising edge because it is synchronized with and taken in the clock.
The reset period can be extended by making the low level period of the reset signal longer because the clock
output pin is fixed to low (reset) during the low level period at the clock rising edge. If the reset start timing is
regarded as not important, the timing where the reset signal is set from high to low is not so consequence.
However, when the reset is released the timing where the reset signal is set from low to high must become
significant because the timing is used to commence the 1/2 frequency-divided clock. In this case, the setup
time (T_rs) is also necessary.
See the timing chart for detail. (This chart shows the example of reset for 2T.)
The A/D converter can operate at Fc (min.) = 160MSPS in this mode.
Straight mode
DMUX mode
Operation
mode
SELECT1
pin
GND
V
CC
Maximum
conversion rate
160MSPS
125MSPS
Table 2. Operation Mode Table
Demultiplexed output
Straight output
Data output
125Mbps
80Mbps
– 12 –
The input clock is 1/2 frequency divided
and output.
The input clock is inverted and output.
Clock output
125MHz
80MHz
CXA3286R