CXA3286 Sony Corporation, CXA3286 Datasheet - Page 19

• Manufacturer Part Number: CXA3286
• Description: 8-bit 160MSPS Flash A/D Converter
• Manufacturer: Sony Corporation

Notes on Operation
• The CXA3286R has the PECL and TTL input pins for the clock and reset input pins. When the clock is input
• The impedance of the input signal should be properly matched to ensure the CXA3286R's stable operation at
• The power supply and grounding have a profound influence on converter performance. The power supply
• The analog input pin V
• The V
• If the CLKN/E pin is not used, by-pass this pin to DGND with an approximately 0.1µF capacitor. At this time,
in PECL level, inputting the reset signal in PECL level is recommended. Also, when the clock is input in TTL
level, inputting the reset signal in TTL is recommended.
the high speed.
and grounding method are particularly important during high-speed operation. General points for caution are
as follows.
— The ground pattern should be as large as possible. It is recommended to make the power supply and
— To prevent interference between AGND and DGND and between AVcc and DVcc, make sure the
— Be sure to turn the analog and digital power supplies on simultaneously. If not simultaneously, the IC does
— Ground the power supply pins (AVcc, DVcc1, DVcc2, DV
— It is recommended to place the ceramic chip capacitor of 0.1µF or more, in particular, between DVcc2
— The digital output wiring should be as short as possible. If the digital output wiring is long, the wiring
proper frequency response, it is necessary to prevent performance deterioration due to parasitic capacitance
or parasitic inductance by using a large capacity drive circuit, keeping wiring as short as possible, and using
chip parts for resistors and capacitors, etc.
to AGND with approximately 1µF tantal capacitor and 0.1µF chip capacitor as short as possible.
approximately DGND3 – 1.2V voltage is generated. However, this is not recommended for use as the threshold
voltage V
ground patterns wider at an inner layer using a multi-layer board.
respective patterns are separated. To prevent a DC offset in the power supply pattern, connect the AVcc
and DVcc lines at one point each via a ferrite-bead filter, etc. Shorting the AGND and DGND patterns in
one place immediately under the A/D converter improves A/D converter performance.
not operate correctly.
0.1µF or larger ceramic chip capacitor.
(Connect the AVcc pin to the AGND pattern and the DVcc1, DVcc2 and DV
and DGND2 with the shortest distance.This has the effect to suppress the noise generated when the
CXA3286R TTL output circuit operates.
capacitance will increase, deteriorating the output slew rate and resulting in reflection to the output
waveform since the original output slew rate is quite fast.
RT
and V
BB
because it is too weak.
RB
pins must have adequate by-pass to protect them from high-frequency noise. By-pass them
IN
has an input capacitance of approximately 10pF. To drive the A/D converter with the
– 19 –
EE
3) as close to each pin as possible with a
EE
3 pins to the DGND pattern.)
CXA3286R