AK4122A AKM [Asahi Kasei Microsystems], AK4122A Datasheet - Page 35

• Manufacturer Part Number: AK4122A
• Description: 24-Bit 96kHz SRC with DIR
• Manufacturer: AKM [Asahi Kasei Microsystems]

■
The DIR of the AK4122A has a Non-PCM steam auto-detection function. In the 32-bit mode when Non-PCM preamble
based on Dolby “AC-3 Data Stream in IEC60958 Interface” is detected, the NPCM bit goes to “1”. The 96-bit sync code
consists of 0x0000, 0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F. Detection of this pattern will set the NPCM bit to “1”.
Once the NPCM bit is set to “1”, it will remain “1” until 4096 frames pass through the chip without an additional sync
pattern being detected (Timing diagram:
preambles Pc and Pd (Pc: burst information, Pd: length code; Refer to
stored to registers. The AK4122A also has a DTS-CD bitstream auto-detection function. When AK4122A detects
DTS-CD bitstream, the DTSCD bit goes to “1”. If the next sync code does not occur within 4096 frames, the DTSCD bit
returns to “0” until either the AK4122A detects the stream again. OR’ed value of the NPCM and DTSCD bits are output
to the AUTO bit. The AK4122A detects 14-bit sync word and 16-bit sync word of a DTS-CD bitstream, and these
detection can be ON/OFF by DTS14 and DTS16 bits.
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The internal registers may be either written or read by the 4-wire μP interface pins: CSN, CCLK, CDTI and CDTO. The
data on this interface consists of Chip address (2bits, C1/0 are fixed to “00”), Read/Write (1bit), Register address (MSB
first, 5bits) and Control data (MSB first, 8bits). Address and data are clocked in on the rising edge of CCLK and data is
clocked out on the falling edge. For write operations, data is latched after the 16th rising edge of CCLK, after a
high-to-low transition of CSN. For read operations, the CDTO output goes to high impedance after a low-to-high
transition of CSN. The maximum speed of CCLK is 5MHz. The chip address is fixed to “00”. Accessing to the chip
address except for “00” is invalid. The PDN pin = “L” resets the registers to their default values. Read/Write operation
can be made without MCLK, BICK and LRCK clocks.
MS1076-E-01
Non-PCM (AC-3, MPEG, etc.) and DTS-CD Bitstream Detection
Serial Control Interface
Write
Read
CSN
CCLK
CDTI
CDTO
CDTI
CDTO
C1 - C0 : Chip Address (Fixed to "00")
R/W :
A4 - A0 : Register Address
D7 - D0 : Control Data
C1
C1
0
READ / WRITE ("1" : WRITE, "0" : READ)
C0
C0
1
R/W
R/W
2
Figure
A4
A4
3
Figure 25. Control I/F Timing
A3
A3
4
27and
Hi-Z
A2
A2
5
Figure
- 35 -
A1
A1
6
Hi-Z
28). When those preambles are detected, the burst
A0
A0
7
D7
D7
Table
8
D6
D6
9
22,
Table
D5
D5
10
D4
D4
11
23) that follow those sync codes are
D3
D3
12
D2
D2
13
D1
D1
14
D0
D0
15
[AK4122A]
Hi-Z
2010/05