MSM9005-XX OKI [OKI electronic componets], MSM9005-XX Datasheet - Page 14
MSM9005-XX
Manufacturer Part Number
MSM9005-XX
Description
DOT MATRIX LCD CONTROLLER WITH 8-DOT COMMON DRIVER AND 65-DOT SEGMENT DRIVER
Manufacturer
OKI [OKI electronic componets]
Datasheet
1.MSM9005-XX.pdf
(30 pages)
- Current page: 14 of 30
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¡ Semiconductor
How to Read Display Data
• Display data is output sequentially from MSB in 8-bit units (MSB first).
• Setting S = "1" by the SOE/D command after setting the CS pin at "H" level enables the output
• Setting the CS pin at "L" level or setting S = "0" by the SOE/D command sets the SO pin to high
• CGARAM or ABRAM data corresponding to the address pointer value is output.
• Display data is output from MSB on the falling edge of the shift clock that is input to the SHT
(Example) Reading by AINC command The wait time of 21 1/f
Address
pointer
of display data from the SO pin.
impedance and disables output of display data.
pin, as shown in the figure below.
Read timing is shown below.
SHT
C/D
SO
CS
SI
1 1 * 0 0 0 0 1
Don't Care
SOE/D command
"HZ"
21 x 1/f
00h
OSC
WAIT
MSB
1
0
Display data at address
00h of CGA RAM
0
0
Don't Care
0
0
AINC command
RD4 RD3 RD2 RD1 RD 0
*
1
21 x 1/f
*
1
OSC
LSB
*
WAIT
MSB
1
0
OSC
Display data at address
01h of CGA RAM
0
0
is required
Don't Care
0
0
AINC command
01h
RD4 RD3 RD2 RD1 RD 0
*
1
FEDL9005-03
MSM9005-xx
*
1
LSB
14/30
*
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