MT8880CE-1 MITEL [Mitel Networks Corporation], MT8880CE-1 Datasheet - Page 12

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MT8880CE-1

Manufacturer Part Number
MT8880CE-1
Description
ISO2-CMOS Integrated DTMFTransceiver
Manufacturer
MITEL [Mitel Networks Corporation]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT8880CE-1
Manufacturer:
TI
Quantity:
2 974
MT8880C/MT8880C-1
4-44
EXAMPLE 1: A software reset must be included at the beginning of all programs to initialize the control
registers after power up. The initialization procedure should be implemented 100ms after power up.
Description
1) Read Status Register
2) Write to Control Register
3) Write to Control Register
4) Write to Control Register
5) Write to Control Register
6) Read Status Register
EXAMPLE 2: Transmit DTMF tones of 50 ms burst/50 ms pause and Receive DTMF Tones
Description
1) Write to Control Register A
2) Write to Control Register B
3) Write to Transmit Data Register
-------------------------------------- wait for an interrupt or poll Status Register ----------------------------------------------
4) Read the Status Register
NOTE: IN THE TX BURST MODE, STATUS REGISTER BIT 1 WILL NOT BE SET UNTIL 100 ms (±2 ms) AFTER THE DATA IS
WRITTEN TO THE TX DATA REGISTER. IN EXTENDED BURST MODE THIS TIME WILL BE DOUBLED TO 200 ms (± 4 ms)
-if bit 1 is set, the Tx is ready for the next tone, in which case...
Write to Transmit Register
(send a digit 5)
-if bit 2 is set, a DTMF tone has been received, in which case....
Read the Receive Data Register
-if both bits are set...
Read the Receive Data Register
Write to Transmit Data Register
(tone out, DTMF, IRQ, Select Control Register B)
(burst mode)
(send a digit 7)
6802
Address
VMA
Data
R/W
IRQ
E
Figure 15 - MT8880C/C-1 to 6802 Interface
Peripheral decode
Figure 16 - Application Hints
ISO
2
-CMOS
CS
CS
+5V
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Control
RS0
RS0
3.3k
1
1
1
1
0
1
0
0
0
0
1
1
1
1
R/W
R/W
1
0
0
0
0
1
0
0
0
1
0
1
1
0
IRQ
RS0
CS
R/W
Data
MT8880C/C-1
b3
b3
2
X
0
0
1
0
X
1
0
0
X
0
X
X
0
Data
b2
b2
X
0
0
0
0
X
1
0
1
X
1
X
X
1
b1
b1
X
0
0
0
0
X
0
0
1
X
0
X
X
0
b0
b0
X
0
0
0
0
X
1
0
1
X
1
X
X
1
.

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