ZL30101QDC ZARLINK [Zarlink Semiconductor Inc], ZL30101QDC Datasheet
ZL30101QDC
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ZL30101QDC Summary of contents
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... RST MODE_SEL1:0 HMS Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved. T1/E1 Stratum 3 System Synchronizer ZL30101QDC Applications • Synchronization and timing control for multi-trunk DS1/E1 systems such as DSLAMs, gateways and PBXs • ...
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Description The ZL30101 Stratum 3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for multi-trunk T1 and E1 transmission equipment. The ZL30101 generates ST-BUS and other TDM clock and framing signals that are phase locked ...
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Change Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Change Summary Changes from June 2004 Issue to October 2004 Issue. Page, section, figure and table numbers refer to this issue. Page Item 1 Text 6 Figure 2 7 Table “Pin Description“ 10 Section 3.2 15 Section 3.4 19 ...
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Physical Description 2.1 Pin Connections F4/F65o F16o AGND IC REF_SEL NC REF0 NC REF1 TIE_CLR BW_SEL Figure 2 - Pin Connections (64 pin TQFP, please see Note 1) Note 1: The ZL30101 uses ...
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Pin Description Pin Description Pin # Name 1 GND Ground Positive Supply Voltage. +1.8 V CORE 3 LOCK Lock Indicator (Output). This output goes to a logic high when the PLL is frequency locked to ...
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Pin Description (continued) Pin # Name 19 RST Reset (Input). A logic low at this input resets the device. On power up, the RST pin must be held low for a minimum of 300 ns after the power supply pins ...
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Pin Description (continued) Pin # Name 43 C8/C32o Clock 8.192 MHz or 32.768 MHz (Output). This output is used for ST-BUS and GCI operation at 8.192 Mbps or for operation with a 32.768 MHz clock. The output frequency is selected ...
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Pin Description (continued) Pin # Name 59 IC Internal Connection. Connect this pin to ground Internal Connection. Connect this pin to ground Positive Supply Voltage. +3 internal bonding Connection. Leave unconnected. ...
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Reference Frequency Detector Precise Frequency REF0 / Monitor REF1 Coarse Frequency Monitor Single Cycle Monitor Exceeding the thresholds of any of the monitors forces the corresponding REF_FAIL pin to go high. The single cycle and coarse frequency failure flags force ...
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C20 Clock Accuracy 0 ppm +4.6 ppm -4.6 ppm -16.6 -15 C20: 20 MHz master clock on OSCi The precise frequency monitor’s failure thresholds are compatible with Telcordia GR-1244-CORE Stratum 3 as shown in Figure 5. It will take the ...
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TIE_CLR = 0 locked to REF0 REF0 REF1 Output Clock locked to REF1 REF0 REF1 Output Clock Figure 6 - Timing Diagram of Hitless Reference Switching The Hitless Mode Switching (HMS) pin enables phase hitless returns from Freerun and Holdover ...
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HMS = 0 Normal mode REF Output Clock Phase drift in Holdover mode REF Output Clock Return to Normal mode REF Output Clock TIE_CLR=0 REF Output Clock Figure 7 - Timing Diagram of Hitless Mode Switching Examples: HMS=1: When 10 ...
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Holdover mode to the Normal mode when a new TIE corrector value is calculated HMS=0: When the same ten Normal to Holdover to Normal mode changes occur ...
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In Normal mode, the DCO provides an output signal which is frequency and phase locked to the selected input reference signal. In Holdover mode, the DCO is free running at a frequency equal to the frequency that the DCO was ...
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Control and Modes of Operation 4.1 Loop Filter Selection The loop filter settings can be selected through the BW_SEL pin, see Table 1. For the ZL30101 to be compliant with Telcordia GR-1244-CORE Stratum 3, BW_SEL must be set low. ...
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The Freerun accuracy of the output clock is equal to the accuracy of the master clock (OSCi output clock is required, the master clock must also be 4.3.2 Holdover Mode Holdover mode is typically used for short ...
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RST (HOLDOVER=1) REF_DIS=1: Current selected reference disrupted (see Figure 3). This is an internal signal. REF_CH= 1: Reference change, a change in the REF_SEL pin. This is an internal signal. 4.4 Reference Selection The active reference input (REF0, REF1) is ...
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REF_SEL LOCK Note: LOCK pin behaviour depends on phase and frequency offset of REF1. Figure 10 - Reference Switching in Normal Mode 5.0 Measures of Performance The following are some PLL performance indicators and their corresponding definitions. 5.1 Jitter Timing ...
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Frequency Accuracy Frequency accuracy is defined as the absolute accuracy of an output clock signal when it is not locked to an external reference, but is operating in a free running mode. 5.6 Holdover Accuracy Holdover accuracy is defined ...
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PLL phase slope limiter, • in-lock phase distance. The presence of input jitter makes it difficult to define when the PLL is locked as it may not be able to align its output to the input within the required ...
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Master Clock The ZL30101 can use either a clock or crystal as the master timing source. Zarlink application note ZLAN-68 lists a number of applicable oscillators and crystals that can be used with the ZL30101. 6.2.1 Clock Oscillator When ...
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Frequency 2 Tolerance 3 Oscillation mode 4 Resonance mode 5 Load capacitance 6 Maximum series resistance Table 6 - Typical Crystal Oscillator Specification ZL30101 6.3 Power Up Sequence The ZL30101 requires that the 3.3 V rail is not powered-up ...
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Reset Circuit A simple power up reset circuit with about a 60 µs reset low time is shown in Figure 14. Resistor R only and limits current into the RST pin during power down conditions. The reset low time ...
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Characteristics 7.1 AC and DC Electrical Characteristics Absolute Maximum Ratings* Parameter 1 Supply voltage 2 Core supply voltage 3 Voltage on any digital pin 4 Voltage on OSCi and OSCo pin 5 Current on any pin 6 Storage temperature ...
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DC Electrical Characteristics* Characteristics 1 Supply current with: OSCi = OSCi = Clock, OUT_SEL=0 3 OSCi = Clock, OUT_SEL=1 4 Core supply current with: OSCi = OSCi = Clock 6 Schmitt trigger Low to ...
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AC Electrical Characteristics* - Input Timing for REF0 and REF1 References (see Figure 16) Characteristics 1 8 kHz reference period 2 1.544 MHz reference period 3 2.048 MHz reference period 4 8.192 MHz reference period 5 16.384 MHz reference period ...
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AC Electrical Characteristics* - Output Timing (see Figure 17) Characteristics 1 C1.5o pulse width low 2 C1.5o delay 3 C2o pulse width low 4 C2o delay 5 F4o pulse width low 6 F4o delay 7 C4o pulse width low 8 ...
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C1.5o C2o F4o C4o F8o C8o F16o C16o F32o C32o F65o C65o F32o, C32o, F65o and C65o are drawn on a larger scale than the other waveforms in this diagram. Figure 17 - Output Timing Referenced to F8/F32o ZL30101 t ...
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AC Electrical Characteristics* - OSCi 20 MHz Master Clock Input Characteristics 1 Oscillator tolerance 2 Duty cycle 3 Rise time 4 Fall time * Supply voltage and operating temperature are as per Recommended Operating Conditions. 7.2 Performance Characteristics Performance Characteristics* ...
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Performance Characteristics*: Output Jitter Generation - ANSI T1.403 Conformance Signal measurement DS1 Interface 1 8 kHz to 40 kHz C1.5o (1.544 MHz kHz * Supply voltage and operating temperature are as per Recommended Operating Conditions. ...
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Zarlink Semiconductor 2002 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in ...