BT8954 CONEXANT [Conexant Systems, Inc], BT8954 Datasheet
BT8954
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BT8954 Summary of contents
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... RS8973, Bt8970 or a Bt8960 DSL Transceiver. The Bt8954 supports clear and compressed voice system. When coupled with a Bt8960, the Bt8954 provides PCM4 functions at greater than 5 km reach with no voice compression, allowing V.34 modem operation. ...
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... Ordering Information Model Number Bt8954 68-Pin Plastic Leaded Chip Carrier (PLCC) Information provided by Conexant Systems, Inc. (Conexant) is believed to be accurate and reliable. However, no responsibility is assumed by Conexant for its use, nor any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of Conexant other than for circuitry embodied in Conexant products ...
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Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Conexant Bt8954 Voice Pair Gain Framer . . . . . . . . . . 4-4 ...
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... Bt8954 Voice Pair Gain Framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 4.8 Common 0xC0—Command Register 1 (CMD_1) 0xC1—Revision Identification (REV_ID 4-18 4 ...
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... A A-4 Conexant Bt8954 Voice Pair Gain Framer N8954DSC ...
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... Bt8954 System Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Figure 2-1. Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Figure 2-2. Bt8954 Functional Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Figure 3-1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Figure 3-2. Basic DSL Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Figure 3-3 ...
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... Output Waveforms for Three-State Enable and Disable Tests . . . . . . . . . . . . . . . . . . . . . . 5-10 Figure 5-13. 68-Pin PLCC Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Figure A-1. Bt8954 to Bt8960/Bt8970 DSL Transceiver Interconnection . . . . . . . . . . . . . . . . . . . . . . . . A-1 Figure A-2. Bt8954 to Texas Instrument TP3054A PCM Codec Interconnection . . . . . . . . . . . . . . . . . . A-2 Figure A-3. Bt8954 to Motorola 68302 Processor Interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3 Figure A-4. Bt8954 to Intel 8051 Controller Interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4 viii Conexant Bt8954 Voice Pair Gain Framer N8954DSC ...
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... Bt8954 Voice Pair Gain Framer List of Tables Table 2-1. Hardware Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Table 3-1. DSL Frame Structure and Overhead Bit Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Table 3-2. 2B1Q Decoder Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Table 3-3 ...
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... List of Tables x Conexant Bt8954 Voice Pair Gain Framer N8954DSC ...
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... The Bt8954 with a higher speed DSL bit pump, such as the Bt8970, allows a greater number of voice conversations to be simultaneously carried over a single twisted pair. The Bt8954/Bt8970 combination can facilitate 64-kbps time slots ...
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... The time-division multiplexing of the voice signals on the PCMT and PCMR serial buses is as follows: Bt8954 informs PCM Codec_n with the PCMFn frame sync when to expect the next byte from Bt8954 on the PCMR bus, and when to put its next byte on the PCMT bus. In this way, Bt8954 uses the PCMFn frame sync to designate the time slot that Codec_n has access to the PCMR and PCMT buses ...
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... Bt8954 Voice Pair Gain Framer Next, EOC and IND overhead are inserted from the Bt8954 EOC and IND registers. The CRC is then calculated and inserted. Then the data is scrambled and transmitted to the destination bit pump. Bt8954 (C R) scrambles like Bt8954 in the Central Office terminal but descrambles like Bt8954 in the remote terminal. That is, SCRAM_TAP = 0 [TCMD2 ...
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... Voice Pair Gain Applications 1.1.2 Subscriber Modem Figure 1-3 Unit (CPU) delivers PCM data directly to Bt8954. Alternatively, a multichannel communications controller such as Bt8472/4 can be used to manage the transfer of data between the CPU and the PCM channel through a local shared memory. Figure 1-3. Subscriber Modem (Terminal) System Block Diagram ...
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... Bt8954 Voice Pair Gain Framer 1.2 System Interfaces System interfaces and associated signals for the Bt8954 functional circuit blocks are illustrated in sections, and signals are defined in Figure 1-4. Bt8954 System Interfaces PCMT ADPCMCK PCMCKO PCM Interface PCMCKI PCMR PCMF[18:1] HCLK PLL IRQ* Microcomputer ...
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... DSL Systems 1.2 System Interfaces 1-6 Conexant Bt8954 Voice Pair Gain Framer N8954DSC ...
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... Pin Descriptions Bt8954 pin assignments for the 68-pin Plastic Leaded Chip Carrier (PLCC) package are illustrated in illustrated in Figure 2-1. Pin Diagram QCLK 10 QCLK_REP 11 12 CS* 13 RD*/DS* 14 WR*/R/W* 15 ALE 16 ADDR[6] VDD 17 GND 18 ADDR[5] 19 ADDR[4] 20 ADDR[ ADDR[2] 23 ADDR[1] ADDR[0] 24 IRQ* 25 GND 26 N8954DSC 2 Figure 2-1. The functional pinout for the Bt8954 is ...
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... Pin Descriptions Figure 2-2. Bt8954 Functional Pinout Motorola/Intel I I Write*/Read/Write I Address Latch Enable I Interrupt Request 28-35 I/O Address Data I 16, 19-24 Address Bus I Reset Chip Select I I Read/Data Strobe Quaternary Clock I Receive Data I Bit Clock I I BCLK Repeater QCLK Repeater I I PCM Transmit Data Input ...
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... Bt8954 Voice Pair Gain Framer Table 2-1. Hardware Signal Definitions ( Pin Pin Label Signal Name Number MOTEL* 36 Motorola/Intel* ALE 15 Address Latch Enable CS* 12 Chip Select RD*/DS* 13 Read/Data Strobe WR*/R/W* 14 Write/Read/Write AD[7:0] 28–35 Address-Data[7:0] ADDR[6:0] 19–24, Address Bus [6:0] 16 (Not Multiplexed) MUXED 37 Addressing Mode Select IRQ* ...
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... The serially encoded 2B1Q sign bit is sampled when QCLK is low, and the 2B1Q magnitude bit is sampled when QCLK is high. I BCLK from the bit pump to which the Bt8954 TDAT is connected in a repeater terminal used only in the repeater mode and should be tied to VDD or GND in non-repeater terminals. ...
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... Bt8954 Voice Pair Gain Framer Table 2-1. Hardware Signal Definitions ( Pin Pin Label Signal Name Number PCMCKO 62 PCM Clock Output PCMCKI 63 PCM Clock Input ADPCMCK 59 ADPCM Clock Output PCMFn 3, PCM Frame Sync (n = 44-51, 1,...,18) 54-58, 65-68 EPCMFn 44-49 Encoded PCM Frame Sync (n = 1,...,6) PCMR 64 PCM Receive Data ...
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... Ground pins for the I/O buffers and core logic functions. Must be held at the same potential as PLL_GND. P Dedicated supply pin for the PLL circuitry. Connect to VDD externally. G Dedicated ground pin for the PLL circuitry. Must be held at the same potential as GND. Conexant Bt8954 Voice Pair Gain Framer N8954DSC ...
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... Figure 3-1. Block Diagram Receiver RDAT 2B1Q Decoder HCLK LB BCLK PLL QCLK 2B1Q TDAT Encoder Transmitter N8954DSC 3 details the major blocks and pins of Bt8954. After the 2B1Q decode of Receive Framer Payload PCM Demux RFIFO OH/Signaling Registers LB Payload PCM Mux TFIFO Microcomputer Interface Microcomputer ...
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... Circuit Descriptions 3.2 DSL Frame Format 3.2 DSL Frame Format The DSL frame is the fundamental data element of the bit streams transmitted and received by Bt8954 at the DSL interface patterned after the 2 T1, 2 E1, and 3 E1 frame structures. Figure 3-2. Basic DSL Frame Format 0 ms ...
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... Bt8954 Voice Pair Gain Framer 3.2.2 Differences Between the DSL and HDSL T1/E1 Frame Formats The DSL frame format is similar to the T1/E1 frame formats that are transported on one HDSL loop. The main difference is due to the number of S-bits. While fixed as 1 F-bit/block and 1 Z-bit/block for the T1 and E1 HDSL frame formats, it can vary between 0 and 8 bits for the DSL frame format ...
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... Embedded Operations Channel crc5–crc6 Cyclic Redundancy Check rta Remote Terminal Alarm rtr Ready to Receive uib Unspecified Indicator Bit uib Unspecified Indicator Bit Payload Blocks 37–48 Conexant Bt8954 Voice Pair Gain Framer DOH Register Bit EOC[3]–EOC[0] — IND[3] IND[2] IND[1] IND[0] N8954DSC ...
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... Bt8954 Voice Pair Gain Framer 3.3 Receiver The receiver performs SYNC word detection, overhead extraction, descrambling of payload data, error performance monitoring, and payload mapping of DSL data from the received DSL frame into the PCM RFIFO. receiver block diagram. The receiver consists of the 2B1Q decoder, receive framer, descrambler, CRC check, and payload demux ...
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... Figure 3-4. Receive Framer Finite State Machine Consecutive SYNC_ACQUIRED states per REACH_SYNC criteria 1 SYNC NO SYNC OUT_OF SYNC NO SYNC NO SYNC 8 Consecutive SYNC_ERRORED states per LOSS_SYNC criteria 3-6 Figure Conexant Bt8954 Voice Pair Gain Framer 3-4. 8 SYNC SYNC IN_SYNC SYNC NO SYNC 1 N8954DSC ...
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... Bt8954 Voice Pair Gain Framer After entering IN_SYNC, the framer either remains IN_SYNC as successive SYNC words are detected or regresses to the SYNC_ERRORED state if SYNC pattern errors are found. During SYNC_ERRORED states, the number of matching bits from each comparison of received SYNC word and the programmed SYNC word pattern must meet or exceed the programmed pattern match tolerance specified by THRESH_CORR [RCMD_2 ...
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... Command register and selects the descrambler algorithm via the DSCRAM_TAP [RCMD_2; 0x91.5,4]. The descrambler, if enabled, descrambles all DSL receive data except the SYNC word. The algorithm is chosen from one of two possible choices, depending on whether Bt8954 is located at the Central Office Remote Site. The descrambler is basically a 23-bit-long Linear Feedback Shift register (LFSR) ...
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... Bt8954 Voice Pair Gain Framer 3.3.5 Payload Demux The Payload Demux block extracts the Indicator (IND), Embedded Operations Channel (EOC), and the S-bits from each receive frame and places them in microcomputer-accessible registers: • Receive Indicator Bits [RIND 0xE2, 0xE3] • Receive Embedded Operations Channel [REOC 0xE0, 0x61] • ...
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... Figure 3-8 details the transmitter block diagram, which consists of SYNC CRC REG OH/Signaling Word Registers CRC Payload MUX 1 1 Scrambler 0 0 RDAT_DESCR DD_LOOP SCRAM_EN Conexant Bt8954 Voice Pair Gain Framer QCLK BCLK 2B1Q TDAT Encoder Stuff Table 3-1, for the OH bit N8954DSC ...
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... Bt8954 Voice Pair Gain Framer 3.4.2 Transmit Signaling FIFOs Using two sets of transmit signaling FIFOs (TSFIFO_I and TSFIFO_O), double buffering ensures that the MC has enough time to write new signaling information without corrupting the signaling information being transmitted, as illustrated in Figure 3-9. Double Buffering, Using Transmit S-Bits Registers ...
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... DSL transmit data except the SYNC word and STUFF bits. The algorithm is chosen from one of two possible choices, depending on whether Bt8954 is located at the Central Office Remote Site. Scrambler Algorithms: The scrambler is basically a 23-bit-long Linear Feedback Shift register (LFSR). The algorithm chosen determines the feedback points ...
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... Bt8954 Voice Pair Gain Framer Figure 3-11. LFSR Structure for Transmission in the Central Office Scrambled Input ( k k-17 z Polynomial xk-23 + xk-5 + 3.4.6 2B1Q Encoder The 2B1Q encoder converts the data to be transmitted to the bit pump into sign and magnitude data according to the quaternary alignment provided on the QCLK input ...
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... COMPRESSED bit configuration in the PCM Format register [0xF1.5]. Only 2:1 ADPCM compression is allowed. Therefore kbps time slot is carrying either kbps of compressed voice or 64 kbps or clear voice. The Bt8954 has a maximum capacity of 18 clear or 36 compressed voice channels. The frame SYNCs are in an encoded or decoded form depending on the ENC_FSYNC bit configuration in PCM_FORMAT [0xF1 ...
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... Bt8954 Voice Pair Gain Framer The PCMF[18:1] (EPCMF[6:1]) waveforms for various scenarios are illustrated in Figure 3-13. PCMF [18:1] Waveforms for Encoded and Decoded Frame SYNC Modes 1) PCM2: 2 Clear Channels PCMCKI (2.048 MHz) PCMF1 PCMF2 PCMF[18:3] Time Slot 1 BYTE1 PCMT/ PCMR 3.9056µs 2) PCM18: 18 Clear Channels PCMCKI (2 ...
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... Circuit Descriptions 3.6 Loopbacks 3.6 Loopbacks Bt8954 provides multiple PCM and DSL loopbacks as illustrated in The output towards which data is looped is called the test direction. Loopback activation in the test direction does not disrupt the through-data path in the non-test direction. initials corresponding to test direction and the channel from which data is looped. ...
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... Bt8954 Voice Pair Gain Framer 3.7 Synchronization All signals are synchronized to TDSL_6ms, RDSL_6ms, TPCM_6ms, and RPCM_6ms. All status registers are synchronized to either TDSL_6ms or RDSL_6ms. The transmitter signals at the DSL (PCM) interface are synchronized to TDSL_6ms (TPCM_6ms). The receiver signals at the DSL (PCM) interface are synchronized to RDSL_6ms (RPCM_6ms) ...
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... PCM transmit frame timing, which in turn is slaved to the DSL receive frame timing at the Remote Site. TFIFO_WL.RT = TFIFO_WL.COT. Figure 3-18. RTF Transmitter Synchronization TPCM_6 ms TDSL_6 ms TFIFO_WL.RT = TFIFO_WL.COT 3-18 Figure 3-17, RPCM_6 ms is phase-offset SYNC_WORD Figure 3-18, TDSL_6ms is phase-offset from Conexant Bt8954 Voice Pair Gain Framer N8954DSC ...
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... Bt8954 Voice Pair Gain Framer 3.7.4 COTF Receiver Synchronization The RDSL_6ms signal in the COTF is generated after SYNC_WORD has been detected as illustrated in RDSL_6ms by RFIFO_WL.RT (RFIFO Water Level in the RTF) plus time to realign to the next TPCM_125 s. At the Central Office, the PCM receive frames are slaved to the DSL frame timing and aligned to the transmit PCM_125 s frame ...
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... The microcomputer interface (MCI) port operating modes, manages overhead protocol, and reads status information from Bt8954. In addition, Bt8954 may signal its need for attention from the microcomputer (MC) by requesting an interrupt. The port can be directly connected to common MCs like the Motorola 68302 or the Intel 8051. ...
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... Bt8954 Voice Pair Gain Framer 3.8.1 Microcomputer Read/Write The MCI provides access to a 128-byte internal address space. depicts the read/write controls. The MCI uses either an 8-bit-wide multiplexed address-data bus (Intel style) or one 8-bit-wide data bus and another separate 7-bit-wide address bus (Motorola style) for external data communications. The interface is configured with the inputs, MOTEL* and MUXED ...
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... RX_ERR = Receive Channel Errors or Framer State Transition to IN_SYNC PLL_ERR = PLL Error LD_TSIG = Load Transmit Signaling Interrupt RD_RSIG = Read Receive Signaling Interrupt SIG_FIFO_ERR = Signaling FIFO Error Interrupt Mask Set Other Interrupt Sources Status Reset Conexant Bt8954 Voice Pair Gain Framer Figure 3-22 and IRQ* N8954DSC ...
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... DFRAME_LEN, SYNC_WORD, CMD_1, PFRAME_LEN, and PCM_FORMAT. This means the f be applied to the RST* pin. When a reset is applied to the RST* pin, the IMR is asynchronously set to a value of 0xFF. The following configuration of the Bt8954 is not valid: N8954DSC must be programmed, and then a reset must PLL ...
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... Circuit Descriptions 3.9 PLL 3.9 PLL The bit pump is the clock master of Bt8954, which in turn is a clock master of the codecs. The PLL synthesizes a variety of (ADPCMCK, PCMCKO) frequency pairs from HCLK (HCLK is 32 times the bit clock, BCLK). the PLL architecture. First, HCLK is scaled by 1/PLL_X in the prescaler to produce f multiple (PLL_INT ...
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... Bt8954 Voice Pair Gain Framer ADPCMCK and PCMCKO are related to BCLK and HCLK through the following equations: The fractional part, FRACP, is scaled as follows: The OUT_OF_LOCK output is the PLL_ERR interrupt. PLL_INT[5:0] bits are in the PLL_INT register [0xB0], FRAC bits are in the PLL_FRAC_HI and PLL_FRAC_LO registers [0xB1 and 0xB2], the A Bit is in the PLL_A register [0xB3], and the B bit is in the PLL_B register [0xB4] ...
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... PLL PLL PLL PLL PLL PLL Conexant Bt8954 Voice Pair Gain Framer Table 3-6. PLL_P bits are also PLL_Y f ADPCMCK PCMCKO 10 2.048 MHz 4 2.048 MHz Max P Freq = f /2 µ GCLK PLL PLL PLL ...
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... Bt8954 Voice Pair Gain Framer Ideally, the Voltage Crystal Oscillator (VCO) should be operated around 200 MHz. Therefore, f factors that synthesize different frequencies for f possible configurations are illustrated. Table 3 204.800 MHz. PLL Table 3-8. Factors for f = 196.608 MHz ( PLL Non-Payload ...
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... Conexant Bt8954 Voice Pair Gain Framer INT FRAC A/B 15 54725 91/97 15 44136 24/49 15 23592 24/25 15 13626 30/101 14 50412 4/13 14 41194 2/35 21 12203 37/145 21 2693 19/73 20 49594 30/37 20 40465 ...
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... Bt8954 Voice Pair Gain Framer Table 3-9. Factors for f = 204.800 MHz ( PLL Non-Payload (kbps) Bit Rate (kHz) 6 384 8 392 16 400 32 416 40 424 64 448 72 456 8 512 8 520 16 528 32 544 40 552 64 576 72 584 12 768 8 776 16 784 32 800 40 808 64 832 72 840 18 1152 ...
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... Circuit Descriptions 3.9 PLL 3-30 Conexant Bt8954 Voice Pair Gain Framer N8954DSC ...
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... Interrupt Status register bits [ISR; 0xD0] to determine when a particular group of registers has been updated. Interrupt-driven and polled procedures must complete reading within the prescribed 1–6 ms interval following DSL frame interrupts. 4.2 Register Groups Bt8954 command, status, and real-time registers are divided into three groups: • Transmit • Receive • Common The group of Transmit and Receive registers only affects operation or reports status of the DSL channel ...
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... Rx FIFO Water Level High PLL_INT PLL_FRAC_HI PLL_FRAC_LO PLL_A PLL_B PLL_SCALE Command Register 1 Revision Identification Interrupt Status Register Interrupt Mask Register Scrambler Reset Transmit FIFO Reset Reset Pointer to Transmit Signaling FIFOs Reset Pointer to Receive Signaling FIFOs Conexant Bt8954 Voice Pair Gain Framer N8954DSC ...
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... Bt8954 Voice Pair Gain Framer Table 4-1. Address Map ( Address Acronym (Hex) 0xD7 RFIFO_RST 0xD8 SYNC_RST 0xD9 ERR_RST 0xDA RX_RST 0xDB UPDATE_TSFIFO_0 0xDC UPDATE_RSFIFO_0 0xE0 REOC_LO 0xE1 REOC_HI 0xE2 RIND_LO 0xE3 RIND_HI 0xE4 RSFIFO_I, RSFIFO_O 0xE5 RSTATUS_1 0xE6 RSTATUS_2 0xE7 TSTATUS_1 ...
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... TIND coincident with the DSL channel’s transmit 6 ms frame interrupt. Unmodified registers repeatedly output their contents in each frame. The most significant bit, TIND[12], is transmitted first. Bt8954 does not automatically output FEBE. Proper transmit of FEBE requires the NOTE copy the CRC_ERR bit from RSTATUS_2 [0xE6] to TIND[1]. ...
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... Bt8954 Voice Pair Gain Framer TIND_LO (Address 0x82 TIND_HI (Address 0x83 — — — 0x84—Transmit Signaling FIFOs (TSFIFO_I, TSFIFO_O) TSFIFO_I[48:1], Employing a double-buffering scheme, two 48-byte FIFOs (transmit signaling input FIFO TSFIFO_O[48:1] [TSFIFO_I] and transmit signaling output FIFO [TSFIFO_0]), transmit signaling information, ...
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... MC access to TSFIFO_I is provided by first writing to TSFIFO_PTR_RST [0xD5] to reset the write pointer, and then writing entries sequentially. TSFIFO_I[1] is written first. Bt8954 increments the TSFIFO_I write pointer after each write cycle to the TSFIFOs address. The pointer wraps around to point to the first entry (TSFIFO_I[1]) after the 48th entry (TSFIFO_I[48]) has been written ...
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... Bt8954 Voice Pair Gain Framer 0x86—Transmit Command Register 1 (TCMD_1) Real-time commands (bits 0–5) are sampled by the OH multiplexer on the respective transmit frame to affect operation in the next outgoing frame. DOH_EN and FORCE_ONE command bit combinations provide the transmit data encoding options needed to perform standard DSL channel start-up procedures. ...
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... S-bits in each TSFIFO and RSFIFO register 0 = HTU-C or LTU terminal type, scrambler taps 5th delay stage 1 = HTU-R or NTU terminal type, scrambler taps 18th delay stage 0 = Bt8954 (C R), scrambler tapes 5th delay stage 1 = Bt8954 (R C), scrambler tapes 18th delay stage 0 = Normal transmit ...
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... Bt8954 Voice Pair Gain Framer 4.5 Receiver Registers One group of registers configures the receiver and controls the mapping of DSL payload bytes into the receiver elastic store (RFIFO). The configuration register defines the DSL receive framer’s criteria for loss and recovery of frame alignment by selecting the number of detected SYNC WORD errors used to declare loss of sync or needed to acquire sync ...
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... DSCRAM_TAP 0 = Disabled testing of RSFIFOs; enabled normal operation 1 = Enabled testing of RSFIFOs; disabled normal operation 0 = Normal receive 1 = RDAT supplied by TDAT Conexant Bt8954 Voice Pair Gain Framer 1 0 THRESH_CORR[3:0] N8954DSC ...
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... Descrambler enabled 0 = HTU-C or LTU terminal type, descrambler selects tap HTU-R or NTU terminal type, descrambler selects tap Bt8954 (R C), scrambler taps 5th delay stage 1 = Bt8954 (C R), scrambler taps 18th delay stage THRESH_CORR SYNC Threshold Correlation 10 or more out of 14 bits ...
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... DSL Frame Length 7 SYNC Word (sign only FIFO Water Level 1 RX FIFO Water Level 4 3 DFRAME_LEN[7: SYNC_WORD[6:0] of the 7-quat (14-bit) transmit and receive SYNC 0 = Negative sign bit 1 = Positive sign bit Conexant Bt8954 Voice Pair Gain Framer N8954DSC ...
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... Bt8954 Voice Pair Gain Framer 0xA2, 0xA3—Rx FIFO Water Level (RFIFO_WL_LO, RFIFO_WL_HI) Receive FIFO Water Level sets the BCLK bit delay from the master DSL channel’s receive 6 ms frame to the PCM receive 6 ms frame. The delay is programmed in BCLK bit intervals, in the range 1024 bits. ...
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... Table 4-5. Bits Name/Description 6 PLL_INT Register 8 MSB of PLL_FRAC 8 LSB of PLL_FRAC 8 PLL_A Register 8 PLL_B Register 7 PLL_X and PLL_C for Pre-Scaling and Post-Scaling /f ratio. PLL REF 4 3 PLL_INT[5: PLL__FRAC_HI[7: PLL__FRAC_LO[7:0] Conexant Bt8954 Voice Pair Gain Framer N8954DSC ...
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... Register (PLL_SCALE) The PLL_SCALE register contains the PLL_X and PLL_C values for pre-scaling the PLL input and for post-scaling the PLL output. PLL_P indicates the maximum microcomputer frequency the Bt8954 supports ( f /2) . For the definitions of PLL_C, PLL_X, and PLL_P, see PLL in Section 3, Circuit Descriptions. ...
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... PCM_FORMAT1 register: 8 < NUM_CHAN < 18) ( PCM1 PCM7 (i.e., for PCM_FORMAT1 register: 1 < NUM_CHAN < Basic DSL frame structure transmit 1 = Transmit extra Z-bit in each block of the DSL frame Conexant Bt8954 Voice Pair Gain Framer Name/Description Command Revision DP_LOOP ...
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... Normal PCM transmit operation 1 = Transmit PCM data supplied by the receiver 0 = Normal PCM receive 1 = PCMR is supplied by PCM transmit input 0 = PCM Sync Master 1 = Receive DSL Sync Master 4 3 — — 000 = Bt8954 Rev A 001 = Bt8954 Rev B 010 = Bt8954 Rev C Conexant 4.0 Registers 4.8 Common VER[2:0] 4-17 ...
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... A LD_TSIG interrupt always occurs coincident with the start of the transmit DSL 6 ms frame, i.e., whenever a Tx interrupt occurs. 4-18 4-7. Bits Name/Description 8 Interrupt Status Register 8 Interrupt Mask Register 4 3 PLL_ERR RX_ERR interrupt 1 = SIG_FIFO_ERR interrupt interrupt 1 = RD_RSIG interrupt interrupt 1 = LD_TSIG interrupt Conexant Bt8954 Voice Pair Gain Framer TX_ERR TX N8954DSC ...
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... Bt8954 Voice Pair Gain Framer PLL Error Interrupt—Indicates if PLL out-of-lock state. PLL_ERR Receive Error Interrupt—Framer state transition to OUT_OF SYNC, RFIFO errors; CRC and RX_ERR FEBE counter overflows are logically ORed to form RX_ERR. Receive DSL 6 ms Frame Interrupt—Reported coincident with the start of the receive DSL frame ...
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... Writing any data value to RSFIFO_PTR_RST resets the pointers to the receive signaling FIFOs. 4-20 Table 4-8. Name/Description Scrambler Reset Transmit FIFO Reset TSFIFO Pointer Reset RSFIFO Pointer Reset Receive FIFO Reset Receive Framer Synchronization Reset Error Count Reset Reset Receiver Update TSFIFO_O Update RSFIFO_O Conexant Bt8954 Voice Pair Gain Framer N8954DSC ...
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... DSL channel’s receive 6 ms frame by reloading the RFIFO_WL value [0xA2, 0xA3]. The MC must write RX_RST after modifying the RFIFO_WL value. Bt8954 automatically performs RX_RST each time the receive framer changes alignment and transitions to the IN_SYNC state, if the EN_AUTO_RFIFO_RST is set. ...
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... Receive Signaling FIFOs Far End Block Error Count 4 3 REOC[7: REOC[12:8] Conexant Bt8954 Voice Pair Gain Framer Receive EOC Bits Receive EOC Bits Receive IND Bits Receive IND Bits Receive Status 1 Receive Status 2 Transmit Status CRC Error Count ...
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... Bt8954 Voice Pair Gain Framer RIND_LO (Address 0xE2 RIND_HI (Address 0xE3 — — — 0xE4—Receive Signaling FIFOs (RSFIFOs) RSFIFO_I[48:1], Employing a double-buffering scheme, two 48-byte FIFOs, receive signaling input FIFO and RSFIFO_O[48:1] (RSFIFO_I), and receive signaling output FIFO (RSFIFO_O) are used to receive signaling information, as illustrated in Figure 4-3 ...
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... MC access to RSFIFO_O is provided by first writing to RSFIFO_PTR_RST [0xC6] to reset the read pointer, and then reading entries sequentially. RSFIFO_O[1] is read first. Bt8954 increments the RSFIFO_O read pointer after read cycle. The pointer wraps around to point to first entry (RSFIFO_O[1]) after the 48th entry (RSFIFO_O[48]) has been read. ...
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... Bt8954 Voice Pair Gain Framer Receive Signaling Input FIFO_UNDER Error—Indicates that RSFIFO_O has underflowed. RSFIFO_O_UNDER That is, RSFIFO_O is being read by the MC faster than it is being updated with RSFIFO_I. Also reported in ISR (as part of SIG_FIFO_ERR) and generates a SIG_FIFO_ERR interrupt (if SIG_FIFO_ERR in IMR is enabled). Receive Signaling Input FIFO_OVER Error—Indicates that RSFIFO_O has overflowed. That RSFIFO_O_OVER is, RSFIFO_O is being updated faster than read by the MC ...
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... CRC pass 1 = CRC error detected 00 OUT_OF_SYNC 01 SYNC_ACQUIRED 10 IN_SYNC 11 SYNC_ERRORED 000 1 frame 001 2 consecutive frames 010 3 consecutive frames 011 4 consecutive frames 100 5 consecutive frames 101 6 consecutive frames 110 7 consecutive frames 111 8 consecutive frames Conexant Bt8954 Voice Pair Gain Framer STATE_CNT[2:0] N8954DSC ...
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... Bt8954 Voice Pair Gain Framer 0xE7—Transmit Status 1 (TSTATUS_1 — — TSFIFO_O_ UNDER Transmit Signaling Output FIFO_UNDER Error—Indicates that the TSFIFO_O has TSFIFO_O_UNDER underflowed. That is, TSFIFO_O is being read into DSL frames faster than it is being updated with TSFIFO_I. Also reported in ISR (as part of SIG_FIFO_ERR), this error generates a SIG_FIFO_ERR interrupt (if SIG_FIFO_ERR in IMR is enabled) ...
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... PCM Formatter The PCM Formatter registers are listed in Table 4-10. PCM Formatter Register Summary Address Register Label 0xF0 PFRAME_LEN 0xF1 PCM_FORMAT 4- CRC_CNT[7: FEBE_CNT[7:0] Table 4-10. Bits Register Description 8 PCM Frame Length 8 PCM Format Conexant Bt8954 Voice Pair Gain Framer N8954DSC ...
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... Bt8954 Voice Pair Gain Framer 0xF0—PCM Frame Length (PFRAME_LEN PCM Frame Length contains the number of bits in one 125 s PCM frame less 1. The selected PFRAME_LEN[7:0] value is given time slots in 125 s PCM frame) –1 if PCM_FREQ (PCM_FORMAT1; addr 0xF1 PFRAME_LEN = –1 = 255 if PCM_FREQ (PCM_FORMAT1 ...
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... Registers 4.12 PCM Formatter 4-30 Conexant Bt8954 Voice Pair Gain Framer N8954DSC ...
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Electrical and Mechanical Specifications 5.1 Electrical Specifications 5.1.1 Absolute Maximum Ratings The absolute maximum ratings are listed in Table 5-1. Absolute Maximum Ratings Symbol Parameter VDD Supply Voltage V Voltage on Any Signal Pin I T Storage Temperature ST ...
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... Table Minimum — = –200 uA 2 — 1 –10 –10 — — — Figures 5-1 Minimum 0.080 Tqclk/2 – 20 Tqclk/2 – Conexant Bt8954 Voice Pair Gain Framer 5-3. Maximum Units 100 mA — V 0.4 V 0.4 V 500 2 ...
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... Bt8954 Voice Pair Gain Framer Table 5-5. DSL Interface Switching Characteristics Symbol Parameter 4 TDAT Setup Prior to BCLK Falling Edge 5 TDAT Hold After BCLK Low 6 BCLK Period 7 BCLK Pulse-Width High 8 BCLK Pulse-Width Low 9 RDAT, QCLK Hold after BCLK Rising Edge 10 RDAT, QCLK Delay after BCLK High Figure 5-2 ...
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... PCMFn (Short Frame Sync) PCMFn+1 (Short Frame Sync) 5-4 Parameter Figure Transmit and Receive Bytes for Codec n Conexant Bt8954 Voice Pair Gain Framer Table 5-6. Minimum Maximum Units 1.536 2.048 MHz — — — — ...
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... Bt8954 Voice Pair Gain Framer 5.1.6 Microcomputer Interface Timing Microcomputer interface timing and switching requirements are displayed in Tables 5-6 and 5-7. MCI write timing, Intel mode (MOTEL = 0) is illustrated in MCI write timing, Motorola mode (MOTEL = 1) is illustrated in MCI read timing, Intel mode (MOTEL = 0) is illustrated in ...
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... Figure 5-4. MCI Write Timing, Intel Mode (MOTEL = 0) Address AD[7: Write Strobe* 20 ALE 5-6 Minimum (1) (1) (1) (1) (2,3) (2,3) (3) (3) (3) Data (Input Conexant Bt8954 Voice Pair Gain Framer Maximum Units 2 — ns — — ns — — ns — QCLK — — ...
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... Bt8954 Voice Pair Gain Framer Figure 5-5. MCI Write Timing, Motorola Mode (MOTEL = 1) Address AD[7: Write Strobe* R/W* 20 ALE Figure 5-6. MCI Read Timing, Intel Mode (MOTEL = 0) Address AD[7: Read Strobe* 20 ALE N8954DSC 5.0 Electrical and Mechanical Specifications Data (Input Data (Output) ...
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... Figure 5-7. MCI Read Timing, Motorola Mode (MOTEL = 1) Address AD[7: Read Strobe* R/W* 20 ALE Figure 5-8. Internal Write Timing Write Strobe* IRQ* Internal Register Internal RAM Access Data Register 5-8 Data (Output Conexant Bt8954 Voice Pair Gain Framer 36 31 N8954DSC ...
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... TDO Enable (Low Z) after TCK Falling Edge 49 TDO Disable (High Z) after TCK Low The Test and Diagnostic Interface of the Bt8954 has not yet been fully characterized; therefore not being tested NOTE(S): according to the VIH, VIL, VOH, and VOL parameters as listed. This interface is for testing only. ...
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... Figure 5-12. Output Waveforms for Three-State Enable and Disable Tests 1.5 V Output Disabled 5-10 Figure 5-10. Output waveforms are Figure 5-11 and Figure 5-12. 2 Input Input Input Low Low High 0 Output Output Low Low V 1 Output Output Disabled Enabled Conexant Bt8954 Voice Pair Gain Framer Output High - 0 0 N8954DSC ...
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... Bt8954 Voice Pair Gain Framer 5.2 Mechanical Specifications The 68-pin PLCC package is illustrated in Figure 5-13. 68-Pin PLCC Package Drawing N8954DSC 5.0 Electrical and Mechanical Specifications 5.2 Mechanical Specifications Figure 5-13. Conexant 5-11 ...
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... Electrical and Mechanical Specifications 5.2 Mechanical Specifications 5-12 Conexant Bt8954 Voice Pair Gain Framer N8954DSC ...
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... Appendix A: Applications This chapter shows typical interconnections of the Bt8954 Voice Pair Gain Framer to the following devices: • Bt8960 MDSL Transceiver or Bt8970 HDSL Transceiver • Texas Instrument TP3054A PCM Codec • Motorola 68302 16-bit Processor • Intel 8051 8-bit Processor A.1 Interfacing to the Bt8960/Bt8970 HDSL ...
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... Appendix A : Applications A.2 Interfacing to the Texas Instrument TP3054A PCM Codec A.2 Interfacing to the Texas Instrument TP3054A PCM Codec A typical interconnection between the Bt8954 and the Texas Instrument TP3054A PCM Codec is illustrated in Figure A-2. Bt8954 to Texas Instrument TP3054A PCM Codec Interconnection Bt8954 A-2 Figure A-2. PCMCLK MCLKX ...
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... Bt8954 Voice Pair Gain Framer A.3 Interfacing to the Motorola 68302 16-Bit Processor A typical interconnection between the Bt8954 and the Motorola 68302 Processor is illustrated in Figure A-3. Bt8954 to Motorola 68302 Processor Interconnection IRQ6* MC68302 A[15] AS* DS* R/W* A[6:0] D[7:0] DTACK* N8954DSC A.3 Interfacing to the Motorola 68302 16-Bit Processor Figure A-3. VDD ...
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... Appendix A : Applications A.4 Interfacing to the Intel 8051 8-Bit A.4 Interfacing to the Intel 8051 8-Bit A typical interconnection between the Bt8954 and the Intel 8051 Controller is illustrated in Figure A-4. Bt8954 to Intel 8051 Controller Interconnection 8051 AD[15] ALE AD[7:0] INT0 A.5 References Applicable specifications are listed here: • Bellcore TA-NWT-001210 • ...