BT8954 CONEXANT [Conexant Systems, Inc], BT8954 Datasheet - Page 66

• Manufacturer Part Number: BT8954
• Description: VOICE PAIR GAIN FRAMER
• Manufacturer: CONEXANT [Conexant Systems, Inc]

4.0 Registers
4.7 PLL Configuration
4.7 PLL Configuration
The PLL synthesizes the PCM clock output (PCMCKO) and the ADPCM clock (ADPCMCK) from the DSL
HCLK (HCLK = 32 x BCLK). Refer to Tables 3-5 through 3-9 on pages 3-25 through 3-28 for the register
values to load into these registers for different BCLK, PCMCLK, and ADPCMCK frequencies. A list of PLL
configuration write registers is displayed in
Table 4-5. PLL Configuration Write Registers
The PLL_INT register contains the integer part of the f
The PLL_FRAC_HI register contains the 8 most significant bits of the PLL_FRAC scaled fraction. For the
definition of PLL_FRAC, see PLL in Section 3, Circuit Descriptions.
The PLL_FRAC_LO register contains the 8 least significant bits of the PLL_FRAC scaled fraction. For the
definition of PLL_FRAC, see PLL in Section 3, Circuit Descriptions.
4-14
0xB0—PLL_INT Register (PLL_INT)
0xB1—PLL_FRAC_HI Register (PLL_FRAC_HI)
0xB2—PLL_FRAC_LO Register (PLL_FRAC_LO)
Address
0xB0
0xB1
0xB2
0xB3
0xB4
0xB5
—
7
7
7
Register Label
PLL_FRAC_LO
PLL_FRAC_HI
PLL_SCALE
PLL_INT
PLL_A
PLL_B
—
6
6
6
5
5
Bits
5
6
8
8
8
8
7
Table
PLL__FRAC_LO[7:0]
PLL__FRAC_HI[7:0]
4
4
4
Conexant
4-5.
PLL
PLL_X and PLL_C for Pre-Scaling and Post-Scaling
/f
REF
3
3
3
ratio.
PLL_INT[5:0]
Name/Description
MSB of PLL_FRAC
LSB of PLL_FRAC
PLL_INT Register
PLL_A Register
PLL_B Register
2
2
2
1
Voice Pair Gain Framer
1
1
N8954DSC
0
Bt8954
0
0